Digital Equipment 21143 Network Adapter Manuals

Manuals and User Guides for Digital Equipment 21143 Network Adapter. We have 1 Digital Equipment 21143 Network Adapter manual available for free PDF download: Reference Manual

Digital Equipment 21143 Reference Manual

Digital Equipment 21143 Reference Manual (260 pages)

PCI/CardBus 10/100-Mb/s Ethernet LAN Controller

Brand: Digital Equipment | Category: Controller | Size: 2 MB

Table of Contents

Table of Contents
3
Preface

17
Introduction

17
- General Description
  17
- Features
  18
- Microarchitecture
  19
- Block Diagram
  21
- Figures
  
  21
Signal Descriptions

23
- 21143 Pinout
  23
- Pinout Diagram (Top View)
  24
Tables

26
- Functional Description of 21143 Signals
  26
Registers

35
Host Communication

101
- Data Communication
  101
- Descriptor Lists and Data Buffers
  101
  - Descriptor Ring and Chain Structure Examples
    102
  - Receive Descriptors
    103
    
    RDES0 Bit Fields
    104
    
    Receive Descriptor 0 (RDES0)
    104
    
    RDES0 Bit Fields Description
    105
    
    RDES1 Bit Fields
    108
    
    RDES1 Bit Fields Description
    108
    
    Receive Descriptor 1 (RDES1)
    108
    
    RDES2 Bit Field
    109
    
    RDES2 Bit Field Description
    109
    
    RDES3 Bit Field
    109
    
    RDES3 Bit Field Description
    109
    
    Receive Descriptor 2 (RDES2)
    109
    
    Receive Descriptor 3 (RDES3)
    109
    
    Receive Descriptor Status Validity
    110
  - Transmit Descriptors
    110
    
    TDES0 Bit Fields
    111
    
    Transmit Descriptor 0 (TDES0)
    111
    
    TDES0 Bit Fields Description
    112
    
    TDES1 Bit Fields
    114
    
    TDES1 Bit Fields Description
    114
    
    Transmit Descriptor 1 (TDES1)
    114
    
    Filtering Type
    116
    
    TDES2 Bit Field
    117
    
    TDES2 Bit Field Description
    117
    
    TDES3 Bit Field
    117
    
    TDES3 Bit Field Description
    117
    
    Transmit Descriptor 2 (TDES2)
    117
    
    Transmit Descriptor 3 (TDES3)
    117
    
    Transmit Descriptor Status Validity
    118
  - Setup Frame
    118
    
    First Setup Frame
    119
    
    Perfect Filtering Setup Frame Buffer
    119
    
    Subsequent Setup Frames
    119
    
    Perfect Filtering Setup Frame Buffer Format
    120
    
    Perfect Filtering Buffer
    121
    
    Imperfect Filtering Setup Frame Buffer
    122
    
    Imperfect Filtering Setup Frame Buffer Format
    123
    
    Imperfect Filtering Buffer
    124
- Functional Description
  127
  - Reset Commands
    127
  - Power-Saving Modes
    128
    
    Sleep Power-Saving Mode
    128
    
    Snooze Power-Saving Mode
    129
  - Arbitration Scheme
    130
  - Arbitration Scheme
    131
- Interrupts
  132
  - Startup Procedure
    133
    
    Descriptor Acquisition
    134
    
    Frame Processing
    134
    
    Receive Process Suspended
    134
    
    Receive Process State Transitions
    136
  - Transmit Process
    137
    
    Frame Processing
    137
    
    Transmit Polling Suspended
    138
Host Bus Operation

141
- Overview
  141
- Bus Commands
  142
- Bus Slave Operation
  142
- Slave Read Cycle (I/O or Memory Target)
  143
- Slave Write Cycle (I/O or Memory Target)
  144
  - Slave Read Cycle
    144
  - Configuration Read and Write Cycles
    145
  - Slave Write Cycle
    145
- Bus Master Operation
  146
- Bus Arbitration
  146
  - Configuration Read Cycle
    146
  - Bus Arbitration
    147
  - Memory Read Cycle
    148
  - Memory Read Cycle
    149
  - Memory Write Cycle
    149
- Termination Cycles
  150
  - Slave-Initiated Termination
    150
    
    Memory Write Cycle
    150
    
    Disconnect Termination
    151
    
    Retry Termination
    152
  - Master-Initiated Termination
    153
    
    21143-Initiated Termination
    153
    
    Normal Completion
    154
    
    Memory-Controller-Initiated Termination
    155
    
    Target Abort
    156
    
    Target Disconnect
    157
- Parity
  158
- Parking
  159
- Parity Operation
  159
Network Interface Operation

161
- MII/SYM Port
  161
  - 100BASE-T Terminology
    161
  - Interface Description
    162
    
    IEEE 802.3 and MII/SYM Signals
    162
    
    Signal Standards
    162
    
    Operating Modes
    164
- 10BASE-T and AUI Functions
  165
  - Receivers and Drivers
    166
  - Manchester Decoder
    166
  - Manchester Encoder
    166
  - Oscillator Circuitry
    166
  - Smart Squelch
    167
  - Autopolarity Detector
    167
  - Crystal Oscillator Specification
    167
  - Network Port Autosensing
    168
  - 10BASE-T Link Integrity Test
    169
- Media Access Control Operation
  169
  - MAC Frame Format
    169
    
    Ethernet and IEEE 802.3 Frames
    170
    
    Ethernet Frame Format Description
    170
    
    Frame Format Table
    171
  - Ethernet Reception Addressing
    172
  - Ethernet Receive Address Groups
    172
  - Detailed Transmit Operation
    173
    
    Transmit Initiation
    173
    
    Frame Encapsulation
    174
    
    Initial Deferral
    174
- Collision
  175
  - Terminating Transmission
    175
  - Transmit Parameter Values
    176
  - Detailed Receive Operation
    177
    
    MII/SYM, 10BASE-T, or AUI Mode Preambles
    177
    
    Preamble Processing
    177
    
    Receive Initiation
    177
    
    100BASE-TX or 100BASE-FX Mode Preambles
    178
    
    Address Matching
    178
    
    Destination Address Bit
    178
    
    Preamble Recognition Sequence in 10BASE-T or AUI Mode
    178
    
    Frame Decapsulation
    179
    
    Terminating Reception
    179
    
    Frame Reception Status
    180
- Loopback Operations
  181
  - Internal Loopback Mode
    181
  - External Loopback Mode
    182
  - Driver Entering Loopback Mode
    182
  - Driver Restoring Normal Operation
    183
- Full-Duplex Operation
  184
- Autonegotiation
  185
- Autonegotiation Modes Selection
  185
- Capture Effect-A Value-Added Feature
  186
- What Is Capture Effect
  186
  - Capture-Effect Sequence
    188
  - Resolving Capture Effect
    188
  - Enhanced Resolution for Capture Effect
    189
- Jabber and Watchdog Timers
  189
- Backoff Algorithm
  189
External Ports

191
- Overview
  191
- Boot ROM and Serial ROM Connection
  191
- Boot ROM, Serial ROM, and External Register Connection
  192
- Boot ROM Operations
  193
  - Byte Read
    193
  - Byte Write
    194
  - Boot ROM Byte Read Cycle
    194
  - Dword Read
    195
  - Boot ROM Byte Write Cycle
    195
  - Boot ROM Dword Read Cycle
    196
- Serial ROM Operations
  197
  - Read Operation
    197
  - Read Cycle
    198
  - Read Cycle
    199
  - Write Operation
    200
  - Write Cycle
    201
  - Write Cycle
    202
- External Register Operation
  203
- LED Description
  204
- General-Purpose Port and Leds
  204
Remotely Waking up the LAN

205
- Overview
  205
- Remote Wake-Up Controller Block Diagram
  205
  - Remote Wake-Up Controller Block Diagram
    206
- Remote Wake-Up-LAN Operation
  207
  - Remote Wake-Up-LAN Mode with Main System Power off
    207
  - Remote Wake-Up-LAN Mode with Main System Power on
    208
- Invalid Password Limiter
  209
- Configuration Revision Register (CFRV-Offset 08H)
  209
- CFRV Register Bit Fields
  210
- CFRV Register Bit Fields Description
  210
- CFRV Register Access Rules
  210
- SIA and General-Purpose Port Register (CSR15-Offset 78H)
  211
- CSR15 Register Bit Fields
  211
- PCI Configuration Registers
  215
- CSR15 Register Access Rules
  215
- Configuration Wake-Up-LAN IEEE Address 0 Register
  216
- Configuration Wake-Up-LAN IEEE Address 1 Register
  218
  - (CWUA1-Offset 48H)
    218
  - CWUA1 Register Bit Fields
    218
  - CWUA1 Register Bit Fields Description
    218
  - CWUA1 Register Access Rules
    218
- Configuration Wake-Up Command Register (CWUC-Offset 54H)
  219
- CWUC Register Bit Fields
  219
- CWUC Register Bit Fields Description
  219
- Secureon™ Password Register (SOP0-Offset 4CH)
  221
- SOP0 Register Bit Fields
  221
- CWUC Register Access Rules
  221
- Secureon Password Register (SOP1-Offset 50H)
  222
- SOP0 Register Bit Fields Description
  222
- SOP0 Register Access Rules
  222
- SOP1 Register Bit Fields
  223
- SOP1 Register Bit Fields Description
  223
- SOP1 Register Access Rules
  223
- Remote Wake-Up-LAN Data Block in the SROM
  224
- Data Block in the SROM
  224
- Remote Wake-Up-LAN IEEE Address and Command (SROM)
  225
- 21143 Magic Packet Format
  228
- Magic Packet Format for the 21143
  228
- Magic Packet Fields
  229
Joint Test Action Group-Test Logic

231
- General Description
  231
- A.1 General Description
  231
- Registers
  232
- Instruction Register
  232
- Bypass Register
  232
  - A.2 Registers
    232
  - A.2.2 Bypass Register
    233
  - Boundary-Scan Register
    233
  - Bypass Register
    233
  - A.2.4 Test Access Port Controller
    234
DNA CSMA/CD Counters and Events Support

235
- CSMA/CD Counters
  235
  - B.1 CSMA/CD Counters
    235
  - CSMA/CD Counters
    236
Hash C Routine

239
- Little Endian Architecture Hash C Routine
  239
- Big Endian Architecture Hash C Routine
  240
Port Selection Procedure

243
- MII Port Selection
  243
- SYM Port Selection
  244
- 10BASE-T Port Selection
  244
- AUI Port Selection
  245
General-Purpose Port and LED Programming

247
- Input Port Selection with Interrupt
  247
- Input Port Selection Without Interrupt
  247
- Output Port Selection
  248
- Led/Control Selection
  248
Support, Products, and Documentation

249

Advertisement

Advertisement

Related Products

Digital Equipment Categories

Desktop

Desktop Server Computer Hardware

Printer

Storage

More Digital Equipment Manuals