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Texas Instruments MSP430F663x Manual
Texas Instruments MSP430F663x Manual

Texas Instruments MSP430F663x Manual

Mixed signal microcontroller
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FEATURES
1
Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultralow Power Consumption
– Active Mode (AM): TBD μA/MHz
– Standby Mode (LPM3 WDT Mode): TBD μA
– Off Mode (LPM4 RAM Retention): TBD μA
– Shutdown Mode (LPM5 RTC Mode): TBD μA
– Shutdown Mode (LPM5): TBD μA
Wake-Up From Standby Mode in Less Than
5 μs
16-Bit RISC Architecture, Extended Memory,
up to 20-MHz System Clock
Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low Power/Low Frequency Internal Clock
Source (VLO)
– Low Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals Up to 32 MHz
(XT2)
16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TA2, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
MIXED SIGNAL MICROCONTROLLER
Two Universal Serial Communication
Interfaces
– USCI_A0 and USCI_A1 Each Supporting
– Enhanced UART supporting
Auto-Baudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1 Each Supporting
2
TM
– I
C
– Synchronous SPI
Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V/1.8-V USB Power System
– Integrated USB-PLL
– Eight Input, Eight Output Endpoints
12-Bit Analog-to-Digital (A/D) Converter With
Internal Shared Reference, Sample-and-Hold,
and Autoscan Feature
Dual 12-Bit Digital-to-Analog (D/A) Converters
With Synchronization
Comparator
Integrated LCD Driver With Contrast Control
for up to 160 Segments
Hardware Multiplier Supporting 32-Bit
Operations
Flash Memory
– Serial Onboard Programming, No External
Programming Voltage Needed
– Enhanced Data Integrity
Six-Channel Internal DMA
Real-Time Clock Module With Supply Voltage
Backup Switch
Family Members are Summarized in
For Complete Module Descriptions, See the
MSP430x5xx/MSP430x6xx Family User's Guide
(SLAU208)
Copyright © 2009, Texas Instruments Incorporated
MSP430F663x
SLAS566 – OCTOBER 2009
Table 1

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Summary of Contents for Texas Instruments MSP430F663x

  • Page 1 PRODUCT PREVIEW information concerns products in the Copyright © 2009, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
  • Page 2 The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 μs. The MSP430F663x series are microcontroller configurations with four 16-bit timers, a high performance 12-bit analog-to-digital (A/D) converter, two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, comparator, USB 2.0, and up to 74 I/O pins.
  • Page 3 TI web site at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package. (3) Product preview. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 4 2 Timer_A Reference Timer_A Timer_B Interface/ 5 CC each with 7 CC 1.5V, 2.0V, Battery 16 Channels 3 CC 2.5V Registers Registers Backup (12 ext/4 int) Port PJ Registers System Autoscan Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 5 6 Channel JTAG/ Comp_B MPY32 CRC16 Segments 2 Timer_A Reference Timer_A Timer_B Interface/ each with 5 CC 7 CC 1.5V, 2.0V, Battery 3 CC 2.5V Registers Registers Backup Port PJ Registers System Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 6: Table Of Contents

    DVSS2 PZ PACKAGE XOUT P8.4 /UCB1CLK/UCA1STE /S11 (TOP VIEW) AVSS2 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/ADC12CLK/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 7 DVSS2 PZ PACKAGE XOUT P8.4 /UCB1CLK/UCA1STE /S11 (TOP VIEW) AVSS2 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/ADC12CLK/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 8 DVSS2 PZ PACKAGE XOUT P8.4 /UCB1CLK/UCA1STE /S11 (TOP VIEW) AVSS2 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 9 MSP430F663x www.ti.com SLAS566 – OCTOBER 2009 Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW ZQW PACKAGE (TOP VIEW) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 10: P6.7/Cb7/A7/Dac1

    General-purpose digital I/O with port interrupt and map-able secondary function P2.5/P2MAP5 Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in (1) I = input, O = output, N/A = not available on this package offering Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 11 Comparator_B output LCD segment output S31 (2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C VCORE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 12 General-purpose digital I/O P8.1/UCB1STE/UCA1CLK/S14 USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output LCD segment output S14 General-purpose digital I/O P8.2/UCA1TXD/UCA1SIMO/S13 USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out LCD segment output S13 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 13: Avss1

    Input terminal for crystal oscillator XT2 General-purpose digital I/O P7.3/XT2OUT Output terminal of crystal oscillator XT2 VBAK Chip internal backup subsystem VBAT Backup supply voltage General-purpose digital I/O P5.7/RTCCLK RTCCLK output DVCC3 Digital power supply Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 14: Avss2

    General-purpose digital I/O P6.3/CB3/A3 Comparator_B input CB3 Analog input A3 – ADC (not available on '6632, '6631, '6630 devices) Reserved BGA package balls. It is recommended to connect to ground Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 15 M(R10) → M(Tab+R6) M(R10) → R11 Indirect auto-increment MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 → R10 Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source, D = destination Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 16 – Complete data retention • Low-power mode 5 (LPM5) – Internal regulator disabled – No data retention – optional RTC clocked by low-frequency oscillator – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 17 The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations SYSTEM...
  • Page 18 MSP430F663x SLAS566 – OCTOBER 2009 www.ti.com Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued) SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY INTERRUPT ADDRESS 0FFC8h ⋮ ⋮ Reserved Reserved 0FF80h 0, lowest (6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatability with other devices, it is recommended to reserve these locations.
  • Page 19 Each sector 0 to n automatically enters low power retention mode when possible. • For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 20 The Backup RAM provides a limited number of bytes of RAM that are retained during LPM5 and during operation from a backup supply in case the Battery Backup System module is implemented. There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
  • Page 21: P2.1/P2Map1

    Oscillator and System Clock The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator XT2.
  • Page 22 WDT timeout (PUC) WDT key violation (PUC) KEYV flash key violation (PUC) FLL unlock (PUC) Peripheral area fetch (PUC) PMM key violation (PUC) EDI Parity Error (PUC) Reserved 24h to 3Eh Lowest Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 23 Reserved 0Ah to 1Eh Lowest No interrupt pending USB wait state timeout Highest SYSBERRIV, Bus Error EDI Error Cache hit (XHIT) 0198h EDI Parity Error (PERR) Reserved 08h to 1Eh Lowest Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 24 DMA1IFG DMA2IFG DMA3IFG DMA4IFG DMAE0 (1) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. (2) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 25: Dvcc1

    The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F663x series includes two complete USCI modules (n = 0 to 1). Timer TA0 Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers.
  • Page 26 CCI1A 44-P3.2 M8-P3.2 DAC12_A CBOUT CCI1B DAC12_0, DAC12_1 (internal) CCR1 TA1.1 (internal) 45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3 ACLK CCI2B (internal) CCR2 TA1.2 (1) Only on devices with peripheral module DAC12_A. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 27 47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5 CCI0B CCR0 TA2.0 48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6 CBOUT CCI1B (internal) CCR1 TA2.1 49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7 ACLK CCI2B (internal) CCR2 TA2.2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 28 TB0.6 CCI6B P2MAPx P2MAPx CCR6 TB0.6 (1) Timer functions selectable via the port mapping controller. (2) Only on devices with peripheral module ADC12_A. (3) Only on devices with peripheral module DAC12_A. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 29 Two hardware triggers/breakpoints on CPU register write access • Up to ten hardware triggers can be combined to form complex triggers/breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 30 000h - 01Fh LCD_B control (refer to Table 0A00h 000h - 05Fh (1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 31 UCS control 1 UCSCTL1 UCS control 2 UCSCTL2 UCS control 3 UCSCTL3 UCS control 4 UCSCTL4 UCS control 5 UCSCTL5 UCS control 6 UCSCTL6 UCS control 7 UCSCTL7 UCS control 8 UCSCTL8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 32 Port P1 interrupt enable P1IE Port P1 interrupt flag P1IFG Port P2 input P2IN Port P2 output P2OUT Port P2 direction P2DIR Port P2 pullup/pulldown enable P2REN Port P2 drive strength P2DS Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 33: Slas566 – October

    P5DS Port P5 selection P5SEL Port P6 input P6IN Port P6 output P6OUT Port P6 direction P6DIR Port P6 pullup/pulldown enable P6REN Port P6 drive strength P6DS Port P6 selection P6SEL Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 34 TA0 counter register TA0R Capture/compare register 0 TA0CCR0 Capture/compare register 1 TA0CCR1 Capture/compare register 2 TA0CCR2 Capture/compare register 3 TA0CCR3 Capture/compare register 4 TA0CCR4 TA0 expansion register 0 TA0EX0 TA0 interrupt vector TA0IV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 35 Capture/compare control 1 TA2CCTL1 Capture/compare control 2 TA2CCTL2 TA2 counter register TA2R Capture/compare register 0 TA2CCR0 Capture/compare register 1 TA2CCR1 Capture/compare register 2 TA2CCR2 TA2 expansion register 0 TA2EX0 TA2 interrupt vector TA2IV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 36 32-bit operand 1 – multiply low word MPY32L 32-bit operand 1 – multiply high word MPY32H 32-bit operand 1 – signed multiply low word MPYS32L 32-bit operand 1 – signed multiply high word MPYS32H Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 37 DMA Channel 3 source address high DMA3SAH DMA Channel 3 destination address low DMA3DAL DMA Channel 3 destination address high DMA3DAH DMA Channel 3 transfer size DMA3SZ DMA Channel 4 control DMA4CTL Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 38 USCI synchronous receive buffer UCB0RXBUF USCI synchronous transmit buffer UCB0TXBUF USCI I2C own address UCB0I2COA USCI I2C slave address UCB0I2CSA USCI interrupt enable UCB0IE USCI interrupt flags UCB0IFG USCI interrupt vector word UCB0IV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 39 ADC12MCTL1 ADC memory-control register 2 ADC12MCTL2 ADC memory-control register 3 ADC12MCTL3 ADC memory-control register 4 ADC12MCTL4 ADC memory-control register 5 ADC12MCTL5 ADC memory-control register 6 ADC12MCTL6 ADC memory-control register 7 ADC12MCTL7 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 40 REGISTER OFFSET Comp_B control register 0 CBCTL0 Comp_B control register 1 CBCTL1 Comp_B control register 2 CBCTL2 Comp_B control register 3 CBCTL3 Comp_B interrupt register CBINT Comp_B interrupt vector word CBIV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 41 LCD_B interrupt vector word LCDBIV 01Eh LCD_B memory 1 LCDM1 020h LCD_B memory 2 LCDM2 021h LCD_B memory 22 LCDM22 035h LCD_B blinking memory 1 LCDBM1 040h LCD_B blinking memory 2 LCDBM2 041h Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...
  • Page 42 MSP430F663x SLAS566 – OCTOBER 2009 www.ti.com Table 49. LCD_B Registers (Base Address: 0A00h) (continued) REGISTER DESCRIPTION REGISTER OFFSET LCD_B blinking memory 22 LCDBM22 055h Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...