Lnterface Circuit; Bcd Digital Interface; Ram/Rom - Datron 1061 Calibration And Servicing Handbook

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BCD DIGITAL INTERFACE (Círcuit
Drawing
No
430332)
The BCD Dig¡tal lnterface
.sre#ly
contains
the
extra memory and
circuitry
required
for
the
execution and
decoding
of
interface functions and
to perform data
output
transfers.
Simplified
diagram, Fig
3'51
shows
the
essential
features
of this
board.
3.12.1
RAM/ROM
Circuit
The BCD
Digital
lnterface assembly
acts
as
an
exten-
sion
to
the Digital
assembly
with
connections
to both
the
Processor
Address
and Data
Buses.
The
board
contains
2k
bytes of program memory (M 111 containing
the sub-routines
to
control the instrument from the
BCD lnterface. Extra
'operating
(scratch pad) memory'
is
provided
by
two 256x4
bit
RAMS
M22,M23l-. Both the
ROM and RAM's
receive
the
address
information,
with
chip
selection being made
by
decoding
address
lines
A8-All
w¡th XIOBD, R/W
and
Ø2.
3.12.2
lnterface
Circuit
The
Peripheral
lnterface Adapter (PlA), M1,
pro-
vides
the
means
of
interfacing
the
BCD
input/output to
the 6800
microprocessor.
The
PIA
is selected
by decoding
address lines A9-41
1
with
XIOBD'
Address lines
A0
and
A1
together with MPU data
messages
configure
the
six
internal
registers
controlling data flow and
external con-
trol
signals.
Peripheral
Data lines
PBO-P87
(Ml
pins
10-17)
are used
as enable
lines
allowing data
to
be placed
on
the
BCD Data Bus
from the
Remote Programming
lnput
and
control
lines
of
the
BCD
Output (2 bytes)
and allowing
data
to
be
placed
ínto output
latches M7-M10' M12-M16
(5
bytes).
,
The
length
of
PRINT COMMAND is controlled
by
the
timer
M2, R1,
C3.
,j::.;
OUTPUT
BU
FFERS
3-STATE
3-STATE
INPUT
BUFFERS
DATA OUT
DATA
LATCHES
DECODE
P87
DO-D7
PIA
PAO
I
PA7
AO-A1
DO.
D7
bvte
OM
2k
R
DO-D7
AO-
256 byte
RAM
FIG.3.51 SIMPLIFIED
DIAGRAM OF
BCD
INTERFACE ASSEMBLY
SOWAY
CONNECTOR
24WAY
CONNECTOR