Write Mode; Read Mode - Datron 1061 Calibration And Servicing Handbook

45
l3
M13/R3/R6/C16
CLOCK
M11
DECODER
M8
BINARY
COUNTER
M9
ADDRESS
LINE
SELECTOR
M1
RAM
Refresh
M4/Ms
BUFFERS
FIG.3.49
SIMPLIFIED
DISPLAY
DRIVER READ
CIRCUITRY
2k{z
9
To
Anode
Drive
C
ircuit ry
(Display
Block
Select l
To Cathode
Drive
Circuitry
(Segment
Select
l
3.10
ç
DISPLAY DR¡VER
ASSEMBLY
(Circuit
Drawing
No.430330).
Basically,
the
Display Driver
assembly
receives
the
display
information from the
m¡croprocessor
(running
at
800kHz) and stores
it
in
a Random Access
Memory (RAM)
digit by digit. This data is then
read
out at a
slower fre-
quency
l2kïzl, level shifted and output
to
the
gas
discharge
display.
)
NOTE: ln
the
following
description,
each
bar,
decimal
point or
legend is
referred
to
as
a
display segment
and each
set
of
segments i.e.
Jl,E
or a
legend
block,
is
referred
to
as
a
disPlaY
block.
3.10.1
Write
Mode
On completion
of
a
reading
or
when certain
modes
are selected, (e.g. ERROR, keyboard
entry), the
processor
indicates
to the
Display
Driver
Board
that data is ready to
be
transferred
by
the
signal
XDDSP (TP6).
This
causes
the RAM
(M'l
) to
be
placed
into
its
write mode
and
the
quadruple
2-line
to
1'line data
selector, Mg,
to
select
the
'B'
inputs which are connected
to
the processor
address
bus.
The
signal XDDSP
also causes
the
tri'state
buffers
M6
and M7
to
become enabled, causíng
the data
input
lines
of the
RAM
to
be
connected
to
the processor
data
bus.
Tirus under MPU control, the display data
(t1,
E
's,
cjecimal
points and
legends)
is written into the
RAM.
Once
this transfer
of
data
is
complete the RAM
be-
comes deselected.
the
buffers
return
to
their
third
state
inhibiting
the data
bus
to the
RAM
and connects the
'A'
3.10.2
Read
Mode
Discharge
between adjacent display blocks is
preven-
ted
by time multiplexing
and
sending
information to
alter-
nate blocks.
A
particular display block
is
selected by
driving
its
anode,
and
a particular
segment
by driving
the
segment
cathode.
The free running
clock
M13, R3,
R5, C16, produces
a
2kHz
signal
(M13-9)
to
drive a 4-bit binary counter,
M8,
which provides
the
control of the
address lines
in the
read
mode
(See
Fig. 3.49). The display block selection
is
achieved
by decoding these
4lines into
16 bits
using M11.
The output lines
of
Mll
are
connected
to
the
bases
of
transistors
01-O3, 013-020 which act
as anode switches.
Note that when the
address
lines
are
in the
state
0000
the output
of Ml1
(pin
11)selects
the
anode
to
block
1,
0001
selects
the
anode
to
block
3 (M11'9),0010...
block
5, etc., thus the display blocks are
selected
alternately.
To
select
the
appropriate segment
data from
the
RAM
to
match
the
display
block
selection
the
address
lines are given a
left
hand^bitlota.tion^
i.e.
if
the
output
of
M8 is
labelled
DCBA,
(2t,2",2',2ul,,
the address
input
of
Ml
would be CBAD. (Fig.3'48
gives the state
of
the
address lines
for
each
display block). The
particular
display
block
segment
data is
recalled
by the
RAM, buffered by
M4 and M5, level
shifted -180
volts
by
R8'R15,
C4-C11
causing
O5-O12
to
drive
the cathodes, D1-D10
acting
as
restoration
diodes. Between the transfer
of
each set of
segment data,
M13'13
is
taken high,
causing
the outputs
of
M4 and M5
to
be
a
logic'0'.
This
produces
a
refresh
period
for
capacitors
C4'C11
to
discharge
from
the -180V supply
through the restoration
diodes.
inputs
of
M9
to the
address
lines
of
the
RAM