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1
*ADSP-21065LCS-240
A
VDD
1
RSF0
2
GND
3
RCLK0
4
DR0A
5
DR0B
6
TFS0
7
TCLK0
8
VDD
9
GND
10
DT0A
11
DT0B
12
RFS1
13
GND
14
RCLK1
15
DR1A
16
DR1B
17
TFS1
18
TCLK1
19
B
VDD
20
VDD
21
DT1A
22
DT1B
23
PWM EVENT1
24
GND
25
PWM EVENT0
26
27
BR1
BR2
28
VDD
29
CLKIN
30
XTAL
31
VDD
32
GND
33
SDCLK1
34
GND
35
VDD
36
SDCLK0
37
DMAR1
38
39
DMAR2
C
HBR
40
GND
41
42
RAS
43
CAS
44
SDWE
45
VDD
DQM
46
SDCKE
47
SDA10
48
GND
49
50
DMAG1
51
DMAG2
52
HBG
D
- Block diagram
DAG1
8x4x32
E
Bus connect
(PX)
F
Multiplier
116
1
2
1
IDENTIFIER
CORE PROCESSOR
Command cash
32x48 bit
DAG2
Program •
8x4x24
sequence
24
PM address bus
32
DM address bus
48
PM data bus
40
DM data bus
Data •
Resistor •
File
16x40 bit
Parallel
ALU
shift
2
3
DUAL PORT SRAM
Dual port block
Processor port
I/O port
ADDR
data
data
ADDR
data
ADDR
10A
17
IOP
Resistor
(memmory map)
Control,
Status,
Timmer and
Data buffer
I/O PROCESSOR
RS-A9/EW
3
4
VDD
156
155
GND
154
GND
153
BMS
BSEL
152
TCK
151
GND
150
TMS
149
148
TDI
147
TRST
146
TDO
145
EMU
ID0
144
ID1
143
NC
142
141
VDD
140
VDD
GND
139
138
FLAG4
FLAG5
137
FLAG6
136
GND
135
134
FLAG7
133
DATA31
132
DATA30
131
VDD
VDD
130
GND
129
128
DATA29
DATA28
127
DATA27
126
GND
125
VDD
124
123
DATA26
122
DATA25
121
DATA24
VDD
120
GND
119
DATA23
118
DATA22
117
DATA21
116
115
NC
GND
114
113
DATA20
112
DATA19
DATA18
111
VDD
110
DATA17
109
108
DATA16
DATA15
107
GND
106
VDD
105
JTAG
7
Test and
emulation
ADDR
data
EXTERNAL
PORT
SDRAM
Interface
10D
48
24
Address Bus
MUX
Multi proccesor
inter face
32
Data bus
MUX
Host port
4
DMA
controller
(2 Rx,2Tx)
SPORT0
2
(I S)
(2 Rx,2Tx)
SPORT1
2
(I S)
4
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