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sizes this is especially relevant in burst mode applications. The SMT340/360/380 will capture data for as
long as the external enable signal is active high.
When configured as a trigger ADC sampling for a specified burst size will be performed each time the
trigger is asserted active. The SMT340/60/80 starts to capture N samples once it detects a rising edge on
the external trigger. The amount of samples to be captured per trigger event (N) is determined by DIP
Switch S2, the amount of blocks to be captured during trigger mode is specified with the LSB 7 bits of S2
(Block size is hardwired to 128 samples).
The user can also select a capture mode where the SMT340/60/80 is permanently enabled irrespective of
the external enable/trigger input.
A FPGA serves as the main controller on the SMT340/60/80. The following functions are implemented
in the FPGA:
§ ADC and Clock Control
§ ADC Data Routing to the SDB connectors
The user can select different data formats to be used, 16-bit sign-extended over one SDB, 16-bit sign-
extended over two SDBs (only SMT380), 8-bit packed over one SDB, 8-bit packed over two SDBs (only
SMT380) or test-words. These output formats are DIP switch selectable, for more detail see section 8.1.
Document Name:
SMT340_360_380_User_Manual_Rev01_Iss01.doc
Document Number:
TBD
Author:
PC Pelser / MR Vogel
Document Title:
SMT340/360/380 User Manual
Preliminary
Revision:
01
Original Date:
25 June 2001
Revision Date:
25 June 2001
Page 9 of 28
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