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5. TECHNICAL DESCRIPTION
Rev01, Issue 01
Ji5/
Input A
Ji6
Ji7/
Input B
Ji8
Ji1/
External clock
Ji2
Ji3/
Ji4
SMT3x0_Block_Rev01_Iss01.vsd
Fig. 1 shows the block diagram of the SMT340/360/380 TIMADC. The following section describes this
family of TIMADCs from a user' s point of view. Reference is made to the different blocks in Fig. 1.
The ADC section implements a high speed Analogue-to-digital converter (12-bit, maximum 105 MHz,
AD9432). ADC Sampling and clock selection is done under control of the FPGA via the Clock Buffering
circuitry.
The Clock Buffering circuitry consists of high-speed differential ECL devices capable of supplying a
very accurate low Jitter differential clock to the ADC. The Clock Buffering circuitry also selects between
the External Clock and onboard Oscillator as the clock source for the ADC.
An external enable/trigger input is available on the SMT340/360/380. Function selection of this signal
between ADC Enable or ADC trigger is done under DIP switch control. When configured as an enable,
ADC Sampling can be selectively enabled (gated) allowing for accurate user control of the data capturing
Document Name:
SMT340_360_380_User_Manual_Rev01_Iss01.doc
Document Number:
TBD
Author:
PC Pelser / MR Vogel
Document Title:
SMT340/360/380 User Manual
Buffer
Buffer
Clock
Control
40MHz,
64MHz or
105MHz
External Enable/Trigger
Fig. 1 : SMT340/360/380 TIM ADC Block diagram
Preliminary
ADC A
Data A
ADC B
Data B
Switch S1
Channel A
Channel B
Control
Jo2 and Jo4 are only
used on the SMT380
Switch S2
Revision:
01
Original Date:
25 June 2001
Revision Date:
25 June 2001
Page 8 of 28
SDB
Jo3
SDB
Jo4
SDB
Jo1
SDB
Jo2
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