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KD-S700GN/KD-S700BU
KD-S7250
PT6523LQ(IC601):LCD DRIVER
1.Pin layout
48 ~ 33
49
32
64
17
1 ~ 16
2.Block diagram
VDD1
VDD2
INH
OSC
DI
CLK
CE
VDD
VSS
3.Pin function
Pin No.
Pin Name
1 ~ 52
SG1 ~ SG52
53 ~ 55
COM1 ~ COM3
56
VDD
57
INH
58
VDD1
59
VDD2
60
VSS
61
OSC
62
CE
63
CLK
64
DI
*Note 1: When INH="LOW" : Serial data transfers can be performed when the display is forcibly OFF.
1-28
COM1 COM2 COM3
COMMON
DRIVER
CLOCK
GENERATOR
ADDRESS
DETECTOR
I/O
O
Segment output pins
Common driver output pins
O
Power supply
-
I
Display OFF control input pin.
When this pin is "LOW", the display is forcibly/turned OFF.
(SG1 to SG52, COM1 to COM3 are set to "LOW").
When this pin is set to "High", the display is ON.
(See Note 1*)
Used for the 2/3 bias voltage when the bias voltages
I
are provided externally. Connect to VDD2 when 1/2 bias
is used.
I
Used for 1/3 bias voltage when the bias voltages are
provided externally. Connect to VDD1 when 1/2 bias
used.
-
Ground pin
I/O
Oscillation Input/Output pin
I
Chip enable pin
I
Synchronization clock
I
Transfer data pin
SG52
SG5 SG4
SG3
SEGMENT DRIVER & LATCH
SHIFT REGISTER
Description
SG2
SG1
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