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SST39VF160 (IC508,509) : 16M EEPROM
1. Pin layout
A15
1
A14
2
A13
3
A12
4
A11
5
A10
6
A9
7
A8
8
A19
9
NC
10
WE#
11
NC
12
NC
13
NC
14
NC
15
A18
16
A17
17
A7
18
A6
19
A5
20
A4
21
A3
22
A2
23
A1
24
2. Block diagram
A19~A0
Address Buffer & Latches
CE#
OE#
WE#
3. Pin function
Symbol
Pin name
A19~A0
Address Inputs
DQ15~DQ0
Data Input/Output
CE#
Chip Enable
OE#
Output Enable
WE#
Write Enable
VDD
Power Supply
Vss
Ground
NC
No Connection
48
A16
47
NC
46
Vss
45
DQ15
44
DQ7
43
DQ14
42
DQ6
41
DQ13
40
DQ5
39
DQ12
38
DQ4
37
VDD
36
DQ11
35
DQ3
34
DQ10
33
DQ2
32
DQ9
31
DQ1
30
DQ8
29
DQ0
28
OE#
27
Vss
26
CE#
25
A0
X-Decoder
Control Logic
Function
To provide memory addresses. During sector erase A19~A11 address
lines will select the sector. During block erase A19~A15 address lines
will select the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are
in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply ( 2.7V-3.6V ).
Unconnected pins.
16,777,216Bit
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ15~DQ0
XV-D721BK
XV-D723GD
1-35
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