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XL-SV320SL/305GD/308BU
ES3207 Pin description
Name
Number
VSS
1,2,25,26,29,30,31,
72,75,77,91,100
VCC
3,4,5,16,32
66,73,78,90
DSC-C
6
AUX[15:0]
40-38,36-34,20,18,
14,67-70,11,9,7
DSC-D[7:0]
81,83,85,93,
95,97,99,8
DSC-S
10
DCLK/
12
EXT-CLK
RST#
13
MUTE
15
MCLK
17
TWS/
SPLLOUT
19
TSD
21
TBCK
22
RWS/
SEL-PLL1
23
RSTOUT#
24
NC
27,28,65,76
RSD/
33
SEL-PLL0
RBCK
37
SER-IN
VSSA
41,50,51,56,57,62,63 I
VREFM
42
VREFP
43
VCCA
44,45,59,60
AOR
46
AOL
47
MIC2
48
MIC1
49
VREF
52
VCM
53
RSET
54
COMP
55
CDAC
58
YDAC
61
VDAC
64
XOUT
71
XIN
74
PCLK
79
PCLK2X
80
HSYNC#
82
VSYNC#
84
YUV[7:0]
86-89,92,94,96,98
1-10
I/O
I
Ground.
I
Voltage supply 5V.
I
Clock for programming to access internal registers.
I/O
Auxiliary control pins.
I
Data for programming to access internal registers.
I
Strobe for programming to access internal registers.
O
Dual-purpose pin. DCLK is the mpeg decoder clock.
I
EXT-CLK is the external clock. EXT-CLK input during bypass PLL mode.
I
Video reset (active low).
O
Audio mute.
I
Audio master clock.
I
Dual-purpose pin. TWS is the transmit audio frame sync.
O
SPLLOUT is the select PLL output.
I
Transmit audio data input.
I
Transmit audio bit clock.
O
Dual purpose pin. RWS is the receive audio frame sync.
I
Pins SEL-PLL[1:0] select the PLL clock frequency for DCLK output.
SEL PLL1
SEL PLL0
0
0
0
1
1
0
1
1
O
Reset output (active low).
No connect. Do not connect to these pins.
O
Dual purpose pin. RSD is the receive audio data input.
I
SEL-PLL0 is the select PLL. See the table for pin no. 23.
O
Dual purpose pin. RBCK is the receive audio bit clock.
I
SER-IN is serial input DSC mode.
0=Parallel DSC mode.
1=Serial DSC mode.
Analog ground.
I
DAC and ADC minimum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
I
DAC and ADC maximum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
I
Analog VCC. 5V.
O
Right channel output.
O
Left channel output.
I
Microphone input 2.
I
Microphone input 1.
I
Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to
analog ground with 0.1µF.
I
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V.
Bypass to analog ground with 47µF electrolytic in parallel with 0.1µF.
I
Full scale DAC current adjustment.
I
Compensation pin.
O
Modulated chrominance output.
O
Y luminance data bus for screen video port.
O
Composite video output.
O
Crystal output.
I
27MHz crystal input.
I/O
13.5MHz pixel clock.
I/O
27MHz (2 times pixel clock).
I/O
Horizontal sync (active low).
I/O
Vertical sync (active low).
O
YUV luminance and chrominance data bus for screen video port.
XL-SV320SL/SV305GD
Definition
DCLK
Bypass PLL (Input Mode)
27MHz (Output Mode)
32.4MHz (Output Mode)
40.5MHz (Output Mode)
XL-SV308BU
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