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¶ Pin Function
Pin No.
Pin Name
1
CLK
2
XTL1
3
XTL2
4
AD0
5
AD1
6
AD2
7
AD3
8
AD4
9
AD5
10
AD6
11
AD7
12
ALE
13
WR
14
RD
15
VDD
16
TXA
17
INT
18
TXCLK
19
EXCLK
20
CS
21
TXD
22
RXD
23
RXCLK
24
ISET
25
RESET
26
VREF
27
RXA
28
GND
I/O
O
Output clock. This pin is the output of the crystal oscillator frequency only in the TSC
73K321.
I
This pin is for the internal crystal oscillator.
I
This pin is for the internal crystal oscillator. XTL2 can also be driven from an external
clock.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I/O
Bidrectional tri-state address/data bus.
I
Address latch enable. The falling edge of ALE latches the address on AD0–AD2 and
the chip select on CS.
I
Write. A low on this informs the TSC 73K321L that data is available on AD0–AD7 for
writing into an internal register. Data is altched on the rising edge of WR.
I
Read. A low request a read of the TSC 73K321L internal registers. Data cannot be
output unless both RD and the latched CS are active or low.
I
Power supply input.
O
Transmit analog output to the phone line.
O
Interrupt. This open drain output signal is used to inform the processor that a detect
flag has occurred. INT will stay low until the processor reads the detect register or
does a full reset.
O
Transmit Clock. TXCLK is always active.
I
External Clock. Used for serial control interface to clock control data in or out of the
TSC 73K321L.
I
Chip select. A low during the falling edge of ALE on this pin allows a read cycle or a
write cycle to occur. The state of CS is latched on the falling edge of ALE.
I
Transmit Digital Data Input. Serial data for transmission is input on this pin. In Asyn-
chronous modes (1200 or 300 baud) no clocking is necessary.
O/
Received Digital Data Output. Serial receive data is available on this pin. The data is
Weak
always valid on the rising edge of RXCLK when in Synchronous mode. RXD will output
pull-up constant marks if no carrier is detected.
O
Receive Clock. A clock which is 16 x 1200, or 16 x 75 in V.23 mode, or 16 x 300 baud
data rate is output in V.21.
I
Chip current reference. Sets bias current for op-amps.
I
Reset. An active high signal high on this pin will put the chip into an inactive state.
The output of the CLK pin will be set to the crystal frequency.
O
An internally generated reference voltage.
I
Received modulated analog signal input from the phone line.
I
System Ground.
Function
TS4
67
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