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1.7.3
1.7.4
Fast 1/0 Subsystem
Interrupt Controller
The interrupt controller co-ordinates all on-board interrupt functions. These
include all internal sources and a number of signals from elsewhere within
the system. The microSP ARC II uses a 4-bit priority encoded interrupt
mechanism. The SLA VIO provides control and priority encoding for all of
the system interrupt sources. For more information about the SP ARCbook
3 interrupts system, see Section 3.2, "Interrupts", on page 3-5.
EBus Interface and Controller
The SLA VIO provides an 8-bit bus called the EB us for a number of slower
auxiliary devices. The EB us interface of the SLA VIO supports the Boot
ROM; the real time clock and SRAM; and the system clock control port.
This is illustrated in Figure 1-5.
1.8
Fast 1/0 Subsystem
The Fast I/0 Subsystem includes the SCSI, parallel and network interfaces.
These are controlled by the NCR89C105 MACIO. This device is a custom
ASIC designed to be operated with the NCR89C100 SLAVIO as a
two-chip set. The key features of the MACIO include:
•
53C90 style SCSI controller (Emulex FASlOOA compatible)
•
7990 style Ethernet controller
•
Parallel port interface
•
Dual 64 byte FIFOs
•
IEEE-1496 SBus DMA controller
This section describes each of these features.
1.8.1
SCSI Controller
1-10
Architecture Overview
The SCSI controller provides a lOMbyte/sec 8-bit interface able to support
up to eight SCSI devices. The SP ARCbook 3 counts as one device, and the
hard disk counts as a second, making it possible to add six external devices.
The SPARCbook 3 is fitted with a 50-pin high density SCSI-2 connector.
For more information, refer to Chapter 5, "SCSI Controller". For
information about the connections, refer to Appendix B, "Connector
Information".
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