Page 1 Series Technical Reference Manual 980327-02...
Page 2 All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trademarks of SPARC International, Inc. The SPARCbook trademark is licensed exclusively to Tadpole Technology, Inc. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc.
Page 3: Table Of Contents
Contents About This Guide ix Document Summary ........... . .x Definitions .
Page 4 1.13 Modem Interface ..........1-14 1.14 Microcontroller Subsystem .
Page 5 Chapter 5 SCSI Controller Connecting SCSI Devices ......... 5-2 NCR53C9X SCSI Controller .
Page 6 8.2.3 SBus Interface ..........8-3 8.2.4 DBRI Programming Model .
Page 7 11.4 RAMDAC ........... 11-21 11.4.1 RAMDAC host interface .
Page 8 viii...
Page 9: About This Guide
About This Guide The SPARCbook 3 Technical Reference Manual is written for the hardware engineer wishing to carry out service or repairs, and at the software engineer wishing to implement hardware drivers. It is assumed that you are familiar with the operation of SPARCbook 3, as detailed in the SPARCbook 3 User Guide, and that you have an understanding of computer hardware.
Page 10: Document Summary
Document Summary The SPARCbook 3 Technical Reference Manual comprises the following chapters: • Chapter 1 , Architecture Overview, discusses the main features of the SPARCbook 3 and introduces the main hardware devices that provide control over the SPARCbook 3’s operations. The internal architecture of SPARCbook 3 is described, showing how the major devices are connected together.
Page 11: Definitions
Deﬁnitions The following conventions are used in the SPARCbook 3 Technical Reference Manual: Logic states The terms clear or low indicate that the signal being discussed is at the logic level ‘0’. The terms set or high indicate that the signal being discussed is at the logic level ‘1’.
Page 12: Solaris Commands
Solaris commands Information displayed on your SPARCbook screen by the Solaris Operating System is shown in font. is also used to Courier Courier describe system utilities and commands. For example: The mail system will inform you when there is incoming mail from another user.
Page 13: Chapter 1 Architecture Overview
Architecture Overview This chapter discusses the architecture of the SPARCbook 3. It describes the main system components and how they are packaged together to deliver workstation-class performance in a compact notebook form factor.
Page 14: Introduction
Introduction Introduction At the heart of the SPARCbook 3 design concept is the Tadpole Advanced Notebook Architecture (ANA). This defines a set of goals and guidelines to which the SPARCbook 3 range of systems are designed. It is a modular...
Page 15: Microcontroller Module
Main Components are fixed together. When the two boards are correctly assembled, the CPU heatsink is brought into contact with the system’s magnesium base casting to provide effective heat dissipation, as shown in Figure 1-1. Inter-Board Connectors CPU Module Base Board System’s Magnesium Base Heatsink...
Page 16: System Architecture
System Architecture System Architecture The SPARCbook 3 system architecture is illustrated in Figure 1-2. Ethernet Ext. Ext. Display Keyboard/Mouse Modem Audio Parallel SCSI Serial ISDN Display ISDN/ RAMDAC Modem MACIO SLAVIO Audio Graphics Controller SBus Base Board TS102 PCMCIA ASIC Sockets Microcontroller Subsystem...
Page 17: Processor
Processor Processor The CPU used in the S3TX is the TurboSPARC and the CPU used in the S3XPand S3GX is the microSPARC II. The TurboSPARC CPU provides the following key features: • SPARC compliant V8 Integer Unit core • SPARC Reference Memory Management Unit •...
Page 18: Main System Buses
Main System Buses Main System Buses The SPARCbook 3 architecture is based around three main buses conventional for SPARC-based workstations. These are the Memory bus which connects the CPU to the main memory; the SBus which connects the CPU to the major I/O devices; and the EBus. 1.5.1 Memory bus The microSPARC II’s integral memory controller is connected to the...
Page 19: Ebus
Main System Buses Weitek P9100 NCR89C105 NCR89C100 TS102 T725FC Graphics Controller SLAVIO MACIO PCMCIA Controller ISDN Controller Data STSX1012 microSPARC II Address Figure 1-4 SBus Connected Devices The microSPARC II provides an SBus Master and Slave interface which enables the I/O devices with integrated DMA capability to gain access to the main memory without encroaching unduly on processor bandwidth.
Page 20: Dram
8Mbytes x 33, 16Mbytes x 33, 32Mbytes x 33, and 64Mbytesx33. This gives a usable memory capacity of up to of 128. The fast processor clock speed used in SPARCbook 3 series computers requires the use of 60ns SIMMS.
Page 21: Slow I/O Subsystem
Slow I/O Subsystem Slow I/O Subsystem The Slow I/O subsystem is managed by an NCR89C105 SLAVIO. The SLAVIO is an application specific integrated circuit (ASIC), designed as part of a two-chip set with the NCR89C100 MACIO, which provides two serial channels, keyboard and mouse ports, an interrupt controller and two counter-timers.
Page 22: Interrupt Controller
Fast I/O Subsystem 1.7.3 Interrupt Controller The interrupt controller co-ordinates all on-board interrupt functions. These include all internal sources and a number of signals from elsewhere within the system. The microSPARC II uses a 4-bit priority encoded interrupt mechanism. The SLAVIO provides control and priority encoding for all of the system interrupt sources.
Page 23: Ethernet Controller
Fast I/O Subsystem 1.8.2 Ethernet Controller The Ethernet controller provides a 10Mbit/sec networking interface. The design features an AT&T serial interface encoder to provide the standard AUI interface through a 26-way high density connector. An AUI cable and an Ethernet transceiver can be used to provide access to other physical Ethernet media, including Thick, Thin and Fiber-optic networks.
Page 24: Graphics And Video Subsystem
Graphics and Video Subsystem Graphics and Video Subsystem The Graphics and Video Subsystem comprises the Weitek P9100 User Interface Controller, an IBM RGB528 palette DAC (RAMDAC), and a framebuffer provided by a 2MByte array of video RAM (VRAM) devices. All display interface configuration is carried out in software. There are no link adjustments.
Page 25: Mk48T08 Rtcram
The battery-backed RAM is used to store system configuration information, such as manufacturing data and Ethernet ID, via Tadpole’s implementation of the OpenBoot firmware. The real time clock provides second, minute, hour, day, date, month and year information and a calibration register which allows adjustment of the RTC function in 2ppm steps.
Page 26: Pcmcia Controller
Microphone and line analog outputs 1.12 PCMCIA Controller The PCMCIA controller is the Tadpole TS102. This device provides an interface between the SBus and the PCMCIA bus. It performs the additional function of providing a serial link between the CPU and microcontroller.
Page 27: Microcontroller Subsystem
Microcontroller Subsystem The modem supports a number of high level functions. It implements DTMF dialing, call progression, and is controlled via an enhanced “AT” command set. The data standards supported include V.22 bis, V.23, V.32, V.32 bis, V.42, and V.42 bis. In addition, the modem provides send and receive Fax capabilities to Group 3 standards (at up to 14,400bps).
Page 28 Microcontroller Subsystem Architecture Overview 1-16...
Page 29: The Sparc Cpu
The SPARC CPU Processing power for all SPARCbook 3 models is provided by SPARC processors. In the case of he S3XP and S3GX microSPARC II is used; in the case of the S3TX TurboSPARC is used. This chapter provides a general overview of SPARC CPU.
Page 30: Sparc Architecture Overview
SPARC Architecture Overview SPARC Architecture Overview The SPARC processor is a highly integrated device which provides the following features: • SPARC compliant V8 Integer Unit core • SPARC Reference Memory Management Unit • MEIKO Floating Point Unit • 16 Kbyte Instruction Cache •...
Page 31: Integer Unit
Integer Unit The SPARC CPU is a RISC (reduced instruction set computer) based processor which uses a simplified command set to carry out operations. It is able to execute most instructions within a single clock cycle. The high performance of the SPARC CPU is enhanced by the ability of the floating point unit (FPU) to execute instructions simultaneously with the integer unit (IU), and by the provision of cache memory.
Page 32: Traps And Interrupts
Integer Unit The arithmetic, logical and shift instructions compute a result that is a function of one or two source operands and then place the result non-destructively in a register. The control transfer instruction category includes jumps, calls, traps, and branches.
Page 33: Memory Protection
Integer Unit The IU supports both asynchronous traps (interrupts) and synchronous traps (error conditions and trap instructions). Traps transfer control to an offset within the trap table. The base address of the table is specified by the Trap Base Register and the offset is a function of the trap type. Traps are taken before the current instruction causes any changes visible to the programmer and can therefore be considered to occur between instructions.
Page 34: Iu Control Registers
Integer Unit LOCALS OUTS LOCALS OUTS LOCALS OUTS GLOBALS Figure 2-2 Window Register Organization window, and is incremented when the processor returns to the previous window. Register windows can be marked as invalid in the WIM register, and interrupts can be enabled to signal when movement into an invalid window is caused by an instruction.
Page 35: Floating Point Unit
Floating Point Unit Floating Point Unit The SPARC FPU is designed to execute all single- and double-precision SPARC Version 8 floating point instructions except fsmuld. All other FP instructions cause an unimplemented floating point operation trap. The FPU contains a 32x32-bit register file. INSTRUCTION fads faddd...
Page 36: Floating Point Registers
Cache Controller and Memory Management Unit 2.3.1 Floating Point Registers The FPU contains thirty-two 32-bit floating-point f registers, as illustrated in Figure 3-8. These form a 32x32-bit register file. The contents of these registers are transferred to and from external memory under control of the IU using floating-point load/store instructions.
Page 37: Translation Lookaside Buffer
Cache Controller and Memory Management Unit 2.4.1 Translation lookaside buffer The Memory Management Unit (MMU) conforms to the standard SPARC architecture definition for memory management. The MMU provides virtual to physical address translation using a translation lookaside buffer (TLB). An entry in the TLB has the fields shown in Figure 2-4.
Page 38 Cache Controller and Memory Management Unit This bit, when set, indicates that a page table pointer is contained in this entry Page Table Field This ﬁeld can contain a PTE, PTP or I/O PTE. It can be read and written using ASI 0x06 (25 bits). Page Table Entry The PTE defines the physical address of a page and its access permission.
Page 39: Address Translation
Cache Controller and Memory Management Unit Page Table Pointer The PTP contains the physical address of a page table in memory, and can be found in the context table, or in a level 1 or 2 page table. Page tables are loaded into the TLB during tablewalks, and are removed by tablewalks or flushing.
Page 40 Cache Controller and Memory Management Unit 24 23 18 17 12 11 Virtual Address Index 1 Index 2 Index 3 Page Offset Context Table Context Table Pointer Register Level 1 Page Table Context Register Root Pointer Level 2 Page Table Level 3 Page Table 12 11...
Page 41 Cache Controller and Memory Management Unit The level at which a table walk terminates (that is, a PTE is found) is related to the size of addressing region associated with the entry. A table walk which finds a PTE in the context table corresponds to a region of 4Gbytes. A PTE corresponds to: a 16Mbyte region in level 1;...
Page 42: Memory Interface
Memory Interface Memory Interface The SPARC provides a 64-bit memory interface which supports up to 128Mbytes of system memory. The memory is composed of four banks of up to 32Mbytes each. Different density devices are supported, allowing the SPARCbook 3 to be fitted with a range of memory size options. The SPARC’s memory interface provides a 64-bit data bus with 2-bit parity (1 bit parity for each 32 bit word).
Page 43: Programmed I/O
SBus Controller 2.8.1 Programmed I/O Programmed I/O transactions consist of an SBus slave cycle only, with address translations being carried out before bus acquisition. The processor executes loads and stores to transfer data between it and devices on the SBus (in I/O Space). The SBus Controller performs write posting during processor writes, allowing processing to continue while the SBus transaction is completed.
Page 44 SBus Controller The SPARC CPU 2-16...
Page 45: Memory Map And Interrupts
Memory Map and Interrupts This chapter describes the addressing architecture and interrupt architecture of SPARCbook 3. The SLAVIO incorporates an interrupt controller and is used to coordinate all on-board interrupts. These include interrupts from devices on the board and interrupts from SLAVIO internal source.
Page 46: Address Map
Address Map Address Map The SBus controller contained in the MicroSPARC partitions the SPARCbook 3’s memory map into a region for the main memory plus five physical address regions of 256Mbytes each for the SBus. The resulting memory map of the SPARCbook is shown in Table 3-1. Address Range Size Region...
Page 47 Address Map The map for SBus Slot 4 is as shwon in Table 3-2. Address Range Size Resource (Hexadecimal) (Mbytes) 78000000 7FFFFFFF MACIO 70000000 77FFFFFF SLAVIO Table 3-2 SBus Slot 4 Memory Map The MACIO provides processor accessible control ports for DMA related operations, for parallel port operations, for SCSI operations and for network interface control.
Page 48 Address Map Offset Range Resource Accessibility (Hexadecimal) 1F00000 1FFFFFF SLAVIO System Controller and Status Register Word 1E00000 1EFFFFF SLAVIO Interrupt Controller Word 1D00000 1DFFFFF SLAVIO Counter/Timers Word, Doubleword 1C00000 1CFFFFF SLAVIO Reserved 1B00000 1BFFFFF SLAVIO Modem Register Byte 1A00000 1AFFFFF SLAVIO Diagnostic Message Register Byte 1900000...
Page 49: Dram
Interrupts 3.1.2 DRAM The DRAM address multiplexers support SIMM units with up to 11 x 11 or (12 x 10) Row/Column multiplex (1Mbit, 4Mbit, and most 16Mbit devices). Each SIMM module can contain one or two banks of memory. SIMM sizes up to 64Mbytes are supported, with a maximum of 32Mbytes per bank.
Page 50 Interrupts The interrupts in SPARCbook 3 can be considered as belonging to three categories: SLAVIO interrupts, MACIO interrupts, and SBus interrupts. The SLAVIO interrupts include those from the internal serial ports and timers and the software interrupts. The MACIO interrupts include the Ethernet, SCSI and parallel port interrupts.
Page 51: Interrupt Control
Interrupts 3.2.1 Interrupt Control The SLAVIO provides a number of interrupts status and control locations. The processor group provides interrupt pending information and control over software interrupts. The system group provides enable and clearing control over the individual hardware interrupt requests. Address (Hexadecimal Device or Register...
Page 52 Interrupts SOFTINT(15:1) Software Interrupt HARDINT(15:1) Hardware Interrupt Interrupt Level 15 Clear Writing a ‘1’ to any of the SOFTINT bits or IC bit in the Interrupt Clear pseudo-register clears the associated interrupt. The Set Soft Int pseudo-register is used to generate software interrupts. Setting a bit in this register sets the associated bit in the pending register and triggers an interrupt request on the appropriate level.
Page 53: Ncr89C105 Slavio Configuration Control
NCR89C105 SLAVIO Configuration Control Bit 17 Reserved Bit 16 E – Ethernet Interrupt Bit 15 Bit S – Serial Port Interrupt (SLAVIO) Bit 14 K – Keyboard/Mouse Interrupt Bits 13:07 SBus IRQ (7:1) Bits 06:00 Reserved NCR89C105 SLAVIO Conﬁguration Control 3.3.1 SLAVIO Conﬁguration Register The NCR89C105 has several software-programmable options which are...
Page 54: Diagnostic Messages
NCR89C105 SLAVIO Configuration Control Bit 2 D - Density Select Source (1 = 82077 density select, 0 = 82077 motor enable #2). - This bit determines which signal drives the external density select pin (FPY_DENSEL). Bit 1 M - Modem Ring Select. When this bit is set to 1, a low on the MSI_IRQ_input causes a level 15 MSI interrupt.
Page 55: Miscellaneous System Functions
NCR89C105 SLAVIO Configuration Control Note All bits in the Diagnostic Message Register are unaffected by system resetbut contains random information after a power-on reset. 3.3.3 Miscellaneous System Functions The NCR89C105 contains two 8-bit Auxiliary I/O Registers: one dedicated to controlling system power-down; and one used to support several hardware functions that do not fit well elsewhere.
Page 56 NCR89C105 SLAVIO Configuration Control Power Down Control (Aux 2) Register Figure 3-6 Auxiliary I/O Register 2 All Bits are cleared to 0 on system reset. Bits 7:6 Reserved. These bits should be masked, and their values should be discarded by the software. These bits can be read and written to, but the values have no meaning or effect.
Page 57 NCR89C105 SLAVIO Configuration Control Modem Register The NCR89C105 can directly support the RI (Ring Indicate) bit output of a modem, when it is configured for modem use. This mode uses the MSI_IRQ_ input pin for sensing modem RI. When the Modem mode and the Modem interrupt are enabled in the Configuration Register, the NCR89C105 generates an SBus level 5 interrupt on RI transitions.
Page 58 NCR89C105 SLAVIO Configuration Control Memory Map and Interrupts 3-14...
Page 59: Serial Interface
Serial Interface The SPARCbook is equipped with two Z85C30 Serial Communications Controllers (SCC), both of which are contained within the SLAVIO. Although packaged in the SLAVIO, the two SCCs appear to software to be fully independent devices. One is a fully functional SCC and one has reduced functionality being intended for keyboard and mouse interfacing.
Page 60: Serial Channel Assignment
Serial Channel Assignment Serial Channel Assignment There are four serial channels on the SPARCbook, which are controlled by SCCs within the SLAVIO. Each channel provides a control interface. Serial Channels A and B are controlled via the Full-Function SCC; the keyboard and mouse port (which is Sun compatible) is controlled via the sub-set SCC.
Page 61: Scc Registers
SCC Registers SCC Registers The SCC internal registers are accessed using a register pointer to perform selection. First, the register pointer bits in WR0 are programmed to specify the register to be accessed. Then, a read or a write is performed at the same address to transfer data into or out of the selected register.
Page 62 SCC Registers Register Function RR15 External/Status interrupt information CRC initialize, mode initialization, Register Pointer Transmit and Receive interrupt, data transfer mode deﬁnitions Interrupt vector (CH A and B) Receive Parameters and controls Transmit and receive parameters and controls Transmit parameters and control Synchronization character or SDLC address ﬁeld Synchronization character or SDLC ﬂag Transmit Buffer...
Page 63 SCC Registers Bit 7 Wait/DMA request enable Bit 6 Wait/DMA request Bit 5 Wait/DMA request on Rx/Tx Bit 4:3 Receive interrupt control 00 = Interrupt disable 01 = Interrupt on ﬁrst char or special condition 10 = Interrupt on all chars or special condition 11 = Interrupt on special condition only Bit 2 Parity as special condition enable...
Page 64 SCC Registers 00 = Sync modes enabled 01 = 1 stop bit/character 10 = 1.5 stop bits/character 11 = 2 stop bits/character Bit 1 Parity Even/Odd Bit 0 Parity enable WR5 – Transmit Bit 7 Parameters and Control Bits 6:5 Bits/character 00 = 5 bits 01 = 7 bits...
Page 65 SCC Registers 00 = NRZ 01 = NRZI 10 = FM1 11 = FM0 Bit 4 Active on poll Bit 3 Mark/Flag on idle Bit 2 Abort/Flag on idle Bit 1 Loop mode Bit 0 6-bit/8-bit Sync WR11 – Clock Mode Bit 7 RTXCb XTAL/No XTAL Control...
Page 66 SCC Registers WR15 – Bit 7 Break/Abort Interrupt enable External/Status Bit 6 Tx Underrun/EOM Interrupt enable Interrupt Control Bit 5 CTS enable Bit 4 Sync/Hunt enable Bit 3 DCD interrupt enable Bit 2 Reserved (write 0) Bit 1 Zero count interrupt enable Bit 0 Reserved (write 0) RR0 –...
Page 67 SCC Registers Bit 3 Channel A EXT/STAT Bit 2 Channel B Rx Bit 1 Channel B Tx Bit 0 Channel B EXT/STAT RR10 – Miscellaneous Bit 7 One clock missing Status Bit 6 Two clocks missing Bit 4 Loop sending Bit 1 On loop Other bits 0...
Page 68: Baud Rate Clocks
Baud Rate Clocks Baud Rate Clocks A 19.66 MHz clock signal generated by the MACIO is used to derive a baud rate clock for all of the SCCs. This is divided by four before being fed to the SCCs at 4.915 MHz. The baud rate can be changed by loading different time constants (which can be different for each channel) into the time constant register.
Page 69: Chapter 5 Scsi Controller
SCSI Controller The MACIO incorporates an enhanced NCR53C90 Fast SCSI Controller (FSC), which supports SCSI-2 operations at up to 10 Mbytes/sec running synchronously. SCSI transfers are supported by the MACIO’s integral DMA controller. SCSI Connector (on I/O Panel) Removable SCSI SCSI Drive MACIO...
Page 70: Connecting Scsi Devices
Connecting SCSI Devices Connecting SCSI Devices The SPARCbook provides a 30-pin high density (Hosiden style) connector, to which you can connect the supplied SCSI adapter cable. This cable provides a 50-way high density SCSI-2 connector that can be used to make connection to SCSI devices.
Page 71 NCR53C9X SCSI Controller Address Register Access 0x788000 Clock Conversion Register 0x788000 Test Mode 0x788000 Conﬁguration 2 Register 0x788000 Conﬁguration 3 Register 0x788000 Transfer Counter High Register Table 5-1 FSC Register Set (Continued) There follows a brief description of the FSC registers. A detailed programming description of the device is beyond the scope of this manual and the user should refer to the bibliography at the rear of this document.
Page 72 NCR53C9X SCSI Controller Command Register Value Command Interrupt Immediate Commands No operation Flush FIFO Reset 53C90A device Reset SCSI bus Disconnect Commands Reselect Sequence Select without ATN sequence Select with ATN sequence Select with ATN and stop sequence Enable Selection / Reselection Disable Selection / Reselection Select with ATN3 Reselect Sequence...
Page 73 NCR53C9X SCSI Controller Status Register The Status register contains the device and interrupt status flags. The Status register should always be read prior to reading the Interrupt Status register which will cause bits to clear. The Status register contains Error, Transfer count and SCSI phase information.
Page 74 NCR53C9X SCSI Controller Bit 1 Selected with ATN Bit 0 Selected Conﬁguration The CON1, CON2 and CON3 registers allow various operating modes to be set up. CON1 is used to control the slow cable mode, parity enable and Registers test, and the 3-bit SCSI host ID. CON2 provides control of the Tagged queuing, group 2 command and parity control facilities provided by the 53C90A.
Page 75: Dma Support
DMA Support DMA Support The SCSI controller is provided with DMA support by one channel of the MACIO integral DMA controller. Between the FSC and Sbus the MACIO provides a 64-byte deep FIFO (D-FIFO) which is bypassed by CPU accesses to the FSC’s registers. 5.3.1 DMA Transfers A transfer from SCSI to memory is carried out in two phases.
Page 76 DMA Support SCSI Controller...
Page 77: Chapter 6 Ethernet Interface
Ethernet Interface The Ethernet interface on the SPARCbook is provided by an NCR92C990 integrated into the MACIO. This provides AUI connections via a 15-pin D-shell connector. The MACIO enhances Ethernet operations by providing DMA support. AT&T T7213 Interface Adapter MACIO NCR 92C990 LAN Controller Sbus...
Page 78: Ncr92C990 Overview
NCR92C990 Overview NCR92C990 Overview The NCR92C990 is a LAN controller which supports the parameters for an IEEE 802.3 network interface. 6.1.1 Bus Interface The LAN controller operates as a bus master or a bus slave device. As a slave, it provides a 16-bit control interface on the SBus with two register locations.
Page 79: Lan Controller Registers
LAN Controller Registers LAN Controller Registers Access to the LAN controller’s internal registers is gained via two 16-bit locations, the Register Data Port (RDP) and Register Address Port (RAP). The RAP is loaded with an index to the required register, and then the register data can be read from or written to the RDP.
Page 80: Control And Status Register 1 And 2
LAN Controller Registers Error – a logical “OR” of BAB, CE, MISS and ME Babble – Transmitter timeout error Collision Error MISS Missed Packet Memory Error – LAN controller unable to access memory as bus master. RINT Receiver Interrupt – set when a packet is received, or if a receive error has occurred.
Page 81: Control And Status Register 3
DMA Support for Network Operations Initialization Block Address (15:1) Initialization Block Address (23:16) Reserved Figure 6-3 Control and Status Registers 1 and 2 6.2.4 Control and Status Register 3 This register is used to set the LAN controller operating parameters to suit its hardware environment.
Page 82 DMA Support for Network Operations Ethernet Interface...
Page 83: Chapter 7 Pcmcia Interface
PCMCIA Interface The PCMCIA inteface is controlled by a custom designed ASIC (application specific integrated circuit), the TS102. The TS102 provides support for two PCMCIA cards and, in addition, an interface between the CPU and microcontroller subsystem which provides battery management, keybaord and mouse interfacing, and initial power sequencing control.
Page 84: Ts102 Architecture Overview
TS102 Architecture Overview TS102 Architecture Overview The general architecture of the TS102 ASIC is illustrated in Figure 8-5. Card A Bus Sizing Interface and FIFO SBus Interface Card B Interface Registers Keybord Port µController Interface Mouse Port Figure 7-2 TS102 Architecture 7.1.1 SBus interface The TS102 provides an IEEE-P1496 compliant 32-bit slave interface, with...
Page 85: Pcmcia Interface
TS102 Architecture Overview The TS102 also features a read-ahead capability. Setting the read-ahead bit in the TS102 card register causes the TS102 to pre-fetch an additional 8 words a of data after each 8 word read from the card, starting from the address used in the last transfer.
Page 86: Ts102 Memory Mapping
TS102 Memory Mapping port status register, and also asserts an interrupt request to the microcontroller. The microcontroller read of the receive register clears the CPU write busy bit and the interrupt request. There is a similar protocol for transfers from the microcontroller to the CPU.
Page 87: Byte Swapping
TS102 Memory Mapping asserts its WAIT signal, the TS102 slave interface responds with a retry acknowledgment to the master, and then continues with the PCMCIA transfer cycle. Similarly, burst accesses to slow PCMCIA cards can cause a single burst access to take longer than 10µs, and in these cases the TS102 responds with a retry acknowledgment.
Page 88: Slavio Expansion Interface
TS102 Memory Mapping with an IOIS16* acknowledgement. The TS102 monitors the IOIS16* signal during I/O accesses in order to decide how many PCMCIA accesses to perform for a given master cycle. 7.2.3 SLAVIO expansion interface The SLAVIO controls access to the boot EPROM and parallel port. It also has an expansion bus that allows additional I/O devices to be added.
Page 89: Ts102 Registers
TS102 Registers intended primarily for recovery from accidental erasure of the boot PROM contents, but may also be used for such applications as field diagnostics, or even OS upgrades. It is also necessary to inhibit the generation of the SBus select to the SLAVIO device when boot redirection is used, in order to prevent the SLAVIO from from responding to accesses that are intended for the PCMCIA interface, while still allowing access to all other SLAVIO...
Page 90: Card A And B Interrupt Registers
TS102 Registers The PCMCIA specification relies on software negotiation between the host system and each card to configure the hardware interface. As a result of this negotiation, some signals on the PCMCIA interface can, if required, be redefined. This is handled via the TS102 register interface. 7.3.1 Card A and B interrupt registers There is one 16 -bit interrupt register for each card.
Page 91: Card Status Register
TS102 Registers I/O cards replace the two battery voltage signals with card status changed and audio waveform input signals. In this case the battery status changed interrupt becomes a card status changed interrupt, and the card status must then be read from the card. 7.3.2 Card status register The card status register contains card status and control bits.
Page 92 TS102 Registers request is not automatically masked when the card is not I/O. The interrupt request should normally be explicitly masked when the card is not I/O using the interurpt mask bit in the card interrupt register. Bit 11 LVL – IRQ Leve/Edge Control. This bit controls whether the card IRQ input is edge or level sensitive.
Page 93: Card Control Register
TS102 Registers 0 = Memory card 1 = I/O card Bit 0 PRES – Present. The PRES bit indicates that both card detects are active and that the card is correctly inserted. 7.3.3 Card Control Register Name Function Asserted Reset Comments AA[25:24] Attribute address A(25:24)
Page 94: Microcontroller Interrupt Register
Microcontroller Registers 7.3.4 Microcontroller Interrupt Register Name Function Asserted Reset TXE_REQ Transmit FIFO empty inter- rupt request TXNF_REQ Transmit FIFO not full inter- rupt request RXNE_REQ Receive FIFO not empty interrupt request RXO_REQ Receive FIFO overﬂow inter- rupt request TXE_MSK Transmit FIFO empty mask TXNF_MSK Transmit FIFO not full mask RXNE_MSK Receive FIFO not empty...
Page 95 Microcontroller Registers The microcontroller has access to TS102 registers within its own address space. The content of these registers and protocols for use are under the control of software programmed into the microcontroller’s onboard ROM during system manufacture. The registers within the microcontroller’s address space are shown in the table below.
Page 96 Microcontroller Registers PCMCIA Interface 7-14...
Page 97: Chapter 8 Isdn And 16-Bit Audio
ISDN and 16-bit Audio The ISDN and 16-bit Audio interfaces on the SPARCbook 3 are provided by a pair of coupled components: the AT&T T7259 Dual Basic Rate ISDN Controller (DBRI); and the Crystal Semiconductor Corporation CS4215 Multimedia Audio Coder-Decoder (CODEC). These provide a terminal endpoint (TE) ISDN interface at the S/T reference point, and also high quality stereo audio.
Page 98: Isdn Overview
ISDN Overview ISDN Overview The integrated services digital network (ISDN) is an advanced telephone system which allows computers to communicate together at a higher data rate than they could using a modem. Information carried on the ISDN is digital and uses a circuit switched system at a basic rate of 64 KB/s on each of two bearer channels, or B channels, and 16 KB/s on a signaling and control channel, or D channel.
Page 99: Te And Nt Ports
DBRI Overview SBus Interface Figure 8-2 DBRI Internal Architecture 8.2.1 TE and NT Ports The TE port provides the basic network connection to the ISDN. The NT port is not used in SPARCbook 3. An internal FIFO buffer is used as a pipe to hold data transfering between interfaces.
Page 100: Dbri Programming Model
DBRI Overview 8.2.4 DBRI Programming Model This section gives a brief overview of the DBRI programming interface. It is not, however, intended to provide a detailed programming guide. The DBRI operates as a coprocessor, maintaining its own data structures in memory and operating on its own instruction set.
Page 101 DBRI Overview Long pipes can be configured to pass data through transparently or to code or decode data as HDLC frames. The CCITT Q921 protocol requires that protocol information is coded as HDLC formatted packets whereas payload data on the B channels does not require processing. In HDLC mode, long pipes perform CRC generation and checking and automatically handle abort conditions.
Page 102 DBRI Overview Time Slots Each of the DBRl's three serial interfaces (CHI, NT and TE) can have time slots defined for them. A time-slot descriptor (TSD) must be assigned to one end of the data pipe in order for data to enter or leave that end of the data pipe via a serial interface Each basic rate interface (BRI) is viewed as a 19-bit long bit string consisting of the B1 and B2 channels (8 bits each), followed by an S or Q...
Page 103: Dbri Internal Registers
DBRI Overview Fixed I/0 Channels S and Q channels are supported on the basic rate interfaces. They can be connected to short data pipes, the other ends of which are in fixed I/O mode. Commands set a value for S and Q which is output repeatedly until changed.
Page 104 DBRI Overview REG0: Status and Bit 15 P – This bit is set by the host or by the DBRI when REG8 (command pointer) is written. It is cleared by the DBRI Control Register when a WAIT command is encountered on the command list.
Page 105 DBRI Overview Bit 1 H – This bit is set and cleared by the host. Setting this bit halts all DMA associated with the long data pipes (these can be delayed) but enables the DBRI to continue execution of commands from the command queue. Any command which controls a data pipe (SDP and DTS commands) is delayed in its execution until the H bit is cleared.
Page 106 DBRI Overview REG2:Parallel I/O This register is associated with parallel I/O port (PIO) operations. Three of the PIO pins are used to control D/C, PDN and RESET pins of the audio Register codec. The bits in this register are assigned as shown in Table 10-6 (all other bits are reserved).
Page 107: Dbri Commands
DBRI Overview 8.2.6 DBRI Commands Control of the DBRI is mainly accomplished using commands. Table 8-2 lists the DBRI command set. Opcode Command Function WAIT Wait command PAUSE Pause command Jump to new command queue Initialize interrupt queue Report execution of command via interrupt Setup data pipe Continue data pipe Deﬁne...
Page 108 DBRI Overview • TE – Set TE interface operating modes. • NT – Set NT interface operating modes. • CDM – Set CHI operating modes. • PAUSE – Pause command execution to allow previous SDP commands to take effect. • CDP –...
Page 109: Data Structures
DBRI Overview 8.2.7 Data structures DBRI instructions, descriptors and transmit and receive data buffers are stored in data structures in main memory. Instruction execution is initiated by loading a pointer to the first instruction into REG8. The DBRI then continues by fetching instructions from data structures in memory. REG8 OP CODE IQ EXTEND POINTER...
Page 110: Audio Codec
Audio CODEC Audio CODEC A Crystal Semiconductor Corporation CS4215 Multimedia Audio Coder-Decoder (CODEC) provides the SPARCbook 3 with stereo audio capabilities. It operates in conjunction with the DBRI with which it is connected via a synchronous serial link. The DBRI’s concentration highway interface (CHI) provides a specialized serial interface which is used to support the audio codec’s operations.
Page 111 Audio CODEC 24.576 MHz XTAL2 16. 9344 MHz XTAL1 CODEC Figure 8-6 Audio Codec Clock Inputs Data transferred between the two devices is assembled into frames carried between the tow devices during times slots specifically assigned to different types of data, as illustrated in Figure 8-7. Time Slot Control Data...
Page 112 Audio CODEC SCLK FSYNC (TSIN) DATA Slot 1 Slot 2 Slot 3 Slot 8 Figure 8-8 Frame Timing The steps required to move the audio codec from data to control mode and then back again are as follows: 1. Lower the output level to maximum attenuation. 2.
Page 113: Control Mode
Audio CODEC 11. Set the D/C line high to place the codec in data mode. The codec will execute an offset calibration cycle 12. Transmit or receive audio data. 8.3.2 Control Mode Conrol information can be written to the audio codec, and status can be read while is is in the control mode.
Page 114 Audio CODEC Data Format Register Bits 5:3 Data conversion frequency. The bits in this ﬁeld are used to select the frequency have the following function: Crystal Source XTAL1 XTAL2 8 kHz 5.5125 kHz 16 kHz 11.025 kHz 27.42857 kHz 18.9 kHz 32 kHz 22.05 kHz 37.8 kHz...
Page 115 Audio CODEC 0 = FSYNC and SCLK tri-sate 12 clock after D/C goes 1 = FSYNC and SCLK tri-sate immediately after D/C goes low Bits 5:4 MCK1:0 – Clock source select 00 = SCLK is master clock, 256 bits per frame. BSEL must be set to 2 and XCLK must be set to 0.
Page 116: Data Mode
Audio CODEC 8.3.3 Data Mode The data mode is used during conversions to pass digital audio data between the DBRI and codec. The frame synchronization rate is equal to the value of the conversion frequency set by the by the DFR bits in the Data Fromat register.
Page 117 Audio CODEC Bit 7 HE – Headphone output enable 0 = Headphone disabled 1 = Headphone enabled Bit 6 LE – Line Output Enable 0 = Line Output disabled 1 = Line Output enabled Bits 5:0 Output attenuation for left channel. LO(5) is MSB. LO(0) represents 1.5 dB.
Page 118 Audio CODEC Intput Setting MA(3:0) RG(3:0) Bits 7:4 MA(3:0) – Monitor path attenuation MA3 is the MSB. MA0 represents 6 dB Full gain is at least 22.5 dB. Not used in mono modes. Bits 3:0 RG(3:0) – Input gain for right channel RG3 is the MSB.
Page 119: Modem
MODEM This chapter discusses the SPARCbook 3’s internal modem. It uses a two-chip set comprising the R65C39 microcontroller unit (MCU) and RC144APL modem data pump (MDP). Connection to a telephone line is made via a data access arrangement (DAA) which provides the required line isolation Figure 9-1 shows the implementation of the modem interface in the SPARCbook 3.
Page 120: Internal Modem Overview
Internal Modem Overview Internal Modem Overview The MCU provides the interface between the host system and DPL. It incorporates a processor core and a 16C450 UART-type parallel interface, and supports an enhanced AT command set as well as Fax Class 2 commands.
Page 121 Interface Control The MCU registers are accessible at base address 0x0F0280000 and are shown in Table 11-1. ADDRESS REGISTER ACCESS 0F0280000 Receive Buffer Read-only Transmit Buffer Write-only Divisor Latch (LSB) Read-Write 0F0280001 Interrupt Enable Read-Write Divisor Latch (MSB) Read-Write 0F0280002 Interrupt Identity Read-only 0F0280003...
Page 122: Modem Registers
Modem Registers Modem Registers This section describes the more significant registers from the point of view of managing the flow of commands and data between main memory and the modem. 9.3.1 Interrupt Enable Register This register contains interrupt control bits. Setting one of the interrupt enable bits has the effect of enabling the associated interrupt request.
Page 123: Line Status Register
AT Command Set 9.3.3 Line Status Register The Line Status register contains information which allows the condition of the transmit and receive buffers to be monitored. Bit 7 Reserved Bit 6 Transmitter Empty This bit when set indicates that both the transmit buffer and the transmit shift register are empty Bit 5 Transmitter Buffer Empty...
Page 124 AT Command Set CODE DESCRIPTION Go Off-hook in Answer Mode Re-execute Previous Command Attention Characters Bell/CCITT Protocol Dial Telephone Number Command Echo Select Line Modulation Switch Hook Control Identiﬁcation Automode Return to Online Set Pulse Dialling Default Quiet Command Reset Code Read/Write From Selected S-Register Set Tone Dialling Default Enable Short-form Result Code...
Page 125 AT Command Set With the exception of A/, all command lines begin with the attention characters “AT” followed by one or more command characters, and are terminated with a . Command lines may contain up to 56 RETURN characters, including A and T. All characters before the AT string, and all characters that follow an errant command are ignored.
Page 126 AT Command Set Echo Command Characters This controls whether the modem echoes command characters back to the host: n = 0 Disable Character Echo n = 1 Enable Character Echo Select Line Modulation This selects line modulation: n = 0 Auto Dial mode n = 1 V.21 or bell 103 (according to Bn)
Page 127 AT Command Set Read S Register This returns the contents of an S register n = S-register Response Format This command is used to select the format of response made by the modem to the host: n = 0 Single Digit Response n = 1 Extended Response Select Extended Response Set...
Page 128 AT Command Set Remote Conﬁguration Password This instructs the modem to store a password. By supplying a matching password, a remote modem may reconfigure the local modem. Supplied by a remote modem. Display Delayed Numbers This causes the modem to send a list of delayed numbers and the delay associated with each.
Page 129: S Registers
S Registers S Registers The SPARCbook modem provides a set of S registers which can be used to control the activity and configuration of the modem, and can be used to obtain status information. A set of default values (or profile) are loaded into these registers during system power-on.
Page 130 S Registers REGISTER FUNCTION Rings to Auto-answer Incoming Ring Counter Escape Character Carriage Return Character Line Feed Character Backspace Character Dial Tone Wait Time Wait Time for Remote Carrier Pause Time for Dial Delay Modiﬁer Carrier Detect Response Time Carrier Loss Disconnection Time DTMF Dialing Speed Escape Guard Time Reserved...
Page 131 S Registers Carriage Return Character Sets the command line and result code terminator character. Pertains to asynchronous operation only. Range: 0-127, ASCII decimal, Default: 13 (Carriage Return) Line Feed Character Sets the character recognized as a line feed. Pertains to asynchronous operation only.
Page 132 S Registers detection of answer tone if allowed by country restrictions. This timer also specifies the wait for silence time of the @ dial modifier in seconds. S7 is not associated with the W dial modifier. Range: 0-255 seconds, Default: 50 Pause Time for Dial Delay Sets the time, in seconds, that the modem must pause when the “.”...
Page 133 S Registers General Bit Mapped Options Indicates the status of command options. Default: 138 (8Ah) (10001010b) Bit 0 This bit is ignored Bit 1 Command echo (En) 0 = Disabled (E0) 1 = Enabled (E 1) (default) Bit 2 Quiet mode (Qn) 0 = Send result codes (Q0) (default) 1 = Do not send result codes (Q1) Bit 3...
Page 134 S Registers 1 = Enabled (&T7) Bit 6 Local analog loopback (LAL) with self test 0 = Disabled (default) 1 = Enabled (&T8) Bit 7 Not used Reserved Test Timer Sets the length of time, in seconds, that the modem conducts a test (commanded by &Tn) before returning to the command line.
Page 135 S Registers Speaker/Results Bit Mapped Options Indicates the status of command options. Default 117 (75h) (01110101b) Bit 0,1 Speaker volume (Ln) 0 = (L0) 1 = Low (L1) (default) 2 = Medium (L2) 3 = High (L3) Bit 2,3 Speaker control (Mn) 0 = Disabled (M0) 1 = Off on carrier (M1) (default) 2 = Always on (M2)
Page 136 S Registers 0 = None (&G0) 1 = None (&G1) 2 = 1800 Hz (&G2) (default) Sleep Inactivity Timer Sets the length of time, in units of 10 seconds, that the modem will operate in normal mode with no detected telephone line DTE line activity before entering low-power sleep mode.
Page 137 S Registers 0 = Dial up line (&L0) (default) 1 = Leased line (&L1) Bit 4,5 Internal clock select (&Xn) 0 = Internal clock (&X0) (default) 1 = External clock (&X1 ) 2 = Slave clock (&X2) Bit 6 CCITT/Bell mode select (Bn) 0 = CCITT mode (B0) (default) 1 = Bell mode (B1) Bit 7...
Page 138 S Registers inoperative in synchronous mode. Range: 0-255 tenths of a second, Default:0 (disabled) Bit Mapped Options Default: 2 (00000010b) Bit 0 Reserved Bit 1 Controls auto line speed detection (Nn) 0 = Disabled (N0) 1 = Enabled (N1) (default) Bit 2, 3 Controls error correction progress messages (Wn)
Page 139 S Registers 4 = An MNP connection is attempted and if it fails, the modem disconnects 5 = An MNP connection is attempted and it fails, Direct mode connection is established 6 = Reserved 7 = An MNP connection is attempted and if it fails, Normal mode connection is established (Default) Bit 3 -7 Reserved...
Page 140 S Registers If S38 is set to 255, the modem does not time-out and continues to attempt to deliver data in the buffer until the connection is lost or the data is delivered. Range: 0-255 seconds, Default: O Flow Control Default: 3 (00000011 b) Bits 0-2 Status of command options...
Page 141 S Registers General Bit Mapped Options Indicates the status of command options. Default: 3 (00000011b) Bits 0 - 1 Compression selection (%Cn) 0 = Disabled (%C0) 1 = MNP5 (%C1) 2 = V.42bis (%C2) 3 = MNP5 and V.42bis (%C2) (default) Bit 2 Auto retrain 0 = Retrains disabled (%E0) (default)
Page 142 S Registers Default: 7 S48=0 Disable negotiation; bypass the detection and negotiation phases; and proceed with LAPM S48 = 7 Enable negotiation (default) S48 = 128 Disable negotiation; bypass the detection and negotiation phases; and proceed at once with the fallback action specified in S36.
Page 143 S Registers S82 = 3 Expedited: Modem sends a break immediately; data integrity is maintained both ahead of and after the break. S82 = 7 Destructive: Modem sends a break immediately; data being processed by each modem at the time of the break is destroyed.
Page 144 S Registers Fax Transmit Level Sets the transmit level, in dBm, for the fax mode. In some countries, this cannot be changed and there are checks to prevent transmit level change. Range: 0 to -15 dBm, Default: 10 Extended Result Code The bits in this register can be set to override some of the Wn command options.
Page 145: Class 2 Fax Command Set
Class 2 Fax Command Set Class 2 Fax Command Set The SPARCbook internal modem is able to execute extended Class 2 Fax Commands, summarized in Table 9-4. These commands must be preceded by the AT characters, and may be terminated with a semicolon (;) or Return COMMAND FUNCTION...
Page 146 Class 2 Fax Command Set MODEM 9-28...
Page 147: Chapter 10 Parallel Interface
Parallel Interface The parallel interface on the SPARCbook is provided by the MACIO. Parallel Port Buffers MACIO Parallel Port Interface / DMA Sbus Figure 10-1 Parallel Port Architecture...
Page 148: Parallel Port Overview
Parallel Port Overview 10.1 Parallel Port Overview The parallel port of the MACIO comprises four 8-bit port registers, three 16-bit configuration registers and a 64 byte FIFO. Parallel communications can be carried out using programmed I/O or DMA operations; the MACIO’s internal DMA controller provides the necessary hardware support.
Page 149: Parallel Port Control Registers
Parallel Port Control Registers sequence of DMA transfers of equal size from different addresses; only the NEXT Address Register need be updated and the DMA controller will simply load its new contents and the existing contents of the NEXT Byte Counter.
Page 150 Parallel Port Control Registers Bit 25 DMA On (read-only) – when set, indicates that DMA transfers are not disabled due to any hardware or software condition. Bit 24 Enable Next (R/W) – when set enables DMA chaining, and autoloading of NEXT registers. Bit 23 Terminal Count Interrupt Disable (R/W) –...
Page 151: Chapter 11 Display Interface
Display Interface This chapter discusses the SPARCbook 3’s display interface. The display interface drives the built-in LCD flat panel display and is able to drive an an external CRT display with resolutions of up to 1600 x 1200 pixels. SPARCbook 3 is able to display simultaneously in the LCD and external display if they operate at the same resolution.
Page 152: Display Interface Overview
Display Interface Overview 11.1 Display Interface Overview VGA(7:0) MD(23:16) Register Selects RGB Video IBM528 Weitek Palette Power 9100 Digital Video Data Random Serial Access Access Port Port Address VRAM Controls 64-bit Pixel Data Figure 11-1 SPARCbook 3 Display Interface Architecture 11.1.1 Architecture The display interface, illustrated in Figure 11-1, is based around two major components, the Weitek Power 9100 User Interface Controller and an IBM...
Page 153: Display Interface Timing
Display Interface Overview The page-mode VRAM device is a type of memory chip specifically designed for use in display memories which provides a read-write random access port through which the CPU and P9100 can perform graphics operations, and a serial port through which image data is output for display by RAMDAC.
Page 154: Lcd Power
Display Interface Overview Pixel clocks The RAMDAC incorporates a programmable pixel clock generator, which allows the pixel clock to be programmed to suit a large range of display formats. In the SPARCbook 3 application, the RAMDAC generates a master pixel clock controlled by values in the Pixel PLL Rate Registers. The master pixel clock is fed into the P9100 which generates the horizontal and vertical synchronization signals.
Page 155: Power 9100 User Interface Controller
Power 9100 User Interface Controller 11.2 Power 9100 User Interface Controller External Display Video/Sync RGB Video/Syncs SVGA RAMDAC Digital Video Parameter Interface Engine Internal Display Drawing Engine VRAM VRAM (Frame Buffer) Power 9100 Control/ Refresh Figure 11-3 Weitek Power 9100 Block Diagram The WEITEK Power 9100 User Interface Controller is an accelerated 2-D graphics processor which supports draw, fill, and bit block-transfer operations at the full speed of the page-mode VRAM employed in...
Page 156: Parameter Engine
Power 9100 User Interface Controller 11.2.1 Parameter engine The parameter engine prepares drawing operations for the drawing engine; its function is to take input coordinates from the host and convert them to a form usable by the drawing engine. The input parameters include the x,y vertices of polygons and the corners of bit block-transfer (BitBlt) regions.
Page 157: Svga Unit
Power 9100 User Interface Controller non-interleaved VRAM modes. These registers are initialized during system startup and but can be reprogrammed discretely via a user interface provided by the NCE Display panel. 11.2.4 SVGA unit The Power 9100 contains an SVGA unit which is functionally independent of the main graphics engine.
Page 158 Power 9100 User Interface Controller Status and control The Power 9100 contains a number of registers which are used to control registers and device operations. They are used, for example, to enable and handle commands interrupts, to control parameter and drawing engine operations and to configure video and VRAM operations.
Page 159: System Control Registers
Power 9100 User Interface Controller Note Due to the behavior of the Weikek Power 9100 chip, writes to any register group must be preceded by a read from the framebuffer with address bits 14:07 matching the register group’s offset. Further accesses to registers within the same group can then be carried out in the normal way.
Page 160 Power 9100 User Interface Controller Bit 25 Reserved Bit 24 Drive Load 2 0 = Normal drive load 1 = Double drive load Bit 23 Clocking – should be zero Bits 22:20 Shift control 0 Bits 19:17 Shift control 1 bits 16:14 Shift control 2 The four shift control ﬁelds are used to deﬁne the resolution,...
Page 161 Power 9100 User Interface Controller Bits 8:3 reserved Bits 2:0 P9100 version Interrupt register This register records events that have triggered an interrupt. A bit when it is asserted to indicate the cause of interrupt stays asserted until cleared by a host write.
Page 162: Video Control Registers
Power 9100 User Interface Controller 0 = Disable Pick interrupts 1 = Enable Pick Interrupts Bits 1:0 Drawing engine idle 0 = Disable drawing engine idle interrupt 1 = Enable drawing engine idle interrupt Alternate Read and These two registers specify the seven high-order address bits when the host Alternate Write Bank uses an alternate apperture to read from or write to the frame buffer.
Page 163 Power 9100 User Interface Controller Address Register Function 38000120 Vertical Length This is used by the host to specify the number of lines in a vertical trace. 38000124 Vertical sync rising edge This register is used to specify where along the vertical trace the rising edge of the horizontal sync signal occurs.
Page 164 Power 9100 User Interface Controller Bit 7 HSYNC Source 0 = External 1 = Internal Bit 6 Reserved - must be set to 0 Bit 5 Enable Video 0 = Blanks asserted, HSYNC and VSYNC are disabled 1= Normal operation Bit 4 Screen repaint mode 0 = Normal...
Page 165: Vram Control Registers
Power 9100 User Interface Controller 11.2.8 VRAM control registers The VRAM control registers specify the timing and chip configuration of the P9100 VRAM interface. These are summarized below: Address Register Function 38000184 Memory Conﬁguration This read-write register speciﬁes how the framebuffer is con- ﬁgured.
Page 166 Power 9100 User Interface Controller Address Function 38003048 32-bit Absolute value for X[1] 38003050 32-bit Absolute value for Y[1] 38003058 16-bit Absolute value for X[1] and 16-bit Absolute value Y[1] 38003068 32-bit Relative value for X[1] 38003070 32-bit Relative value for Y[1] 38003078 16-bit Relative value for X[1] and 16-bit Absolute value Y[1] 38003088...
Page 167 Power 9100 User Interface Controller Bit 4 1 = Quad exception, operation must be done in software Bit 3 1 = Requested quad is concave Bit 2 1= Source coordinates for quad draw entirely outside clipping window Bit 1 1= Source coordinates for quad draw entirely inside clipping window Bit 0 1= Source coordinates for quad draw straddle clipping...
Page 168: 10Drawing Engine Registers
Power 9100 User Interface Controller Register Out of Range (oor) x_oor y_oor x[3] x[2] x[1] x[0] y[3] y[2] y[1] y[0] X Clip x less than min x greater than max x[3] x[2] x[1] x[0] x[3] x[2] x[1] x[0] Y Clip y less than min y greater than y[3]...
Page 169 Power 9100 User Interface Controller Address Name Function 38002280 Pattern [0] 38002284 Pattern [1] Used to specify the pattern for a quad ﬁll. 38002288 Pattern [2] 3800228C Pattern [3] 38002290 User [0] 38002294 User [1] User deﬁned registers 38002298 User [2] 3800229C User [3] 380022A0...
Page 170: 11Ramdac Register Accesses
Direct frame buffer access Bits 15:13 Reserved (contains zeroes) Bits 12:00 Minimum or Maximum y values 11.2.11 RAMDAC register accesses Accesses to the RAMDAC’s internal registers are made through locations within the Power 9100’s address space, see Section 11.4.1, “RAMDAC host interface”, on page 11-22 11.3 Direct frame buffer access...
Page 171: Ramdac
RAMDAC sizes of display: a 640x480 pixel display using 8 bits per pixel; and a 1024 x 900 display using 16 bits per pixel. The framebuffer is considered in the illustration as a rectangular area with a horizontal dimension equivalent to the horizontal resolution of the display.
Page 172: Ramdac Host Interface
RAMDAC 11.4.1 RAMDAC host interface The RAMDAC host interface is mapped through the RAMDAC space of the P9100 at 0x38000200. In response to addresses in the RAMDAC region, the Power 9100 generates register select signals to select the target register. The RAMDAC provides a byte-wide control interface allowing control registers and color lookup tables to be accessed.
Page 173 RAMDAC register at 0x38000220 and the value 0x00 would be written into the Index High register at 0x38000228, and then the read enable register could be accessed at 0x38000230. The column ‘CONTENTS’ shows the values which must be used for the SPARCbook 3 to operate correctly.
Page 174 RAMDAC Register Contents Order Accessed Index Name 8 BPP 16 BPP 24 BPP 32 BPP 000F Buffer A/B Select 0010 Pixel PLL Control 1 0011 Pixel PLL Control 2 0x00 0012 - 0013 Reserved 0014 Fixed Pixel PLL Reference Divider 0x05 (Manditory for 10 MHz) 0015 System PLL Reference Divider...
Page 175 RAMDAC Register Contents Order Accessed Index Name 8 BPP 16 BPP 24 BPP 32 BPP 0035 Cursor X Hotspot 0036 Cursor Y Hotspot 0037 - 003F Reserved 0040 Cursor Color 1 Red 0041 Cursor Color 1 Green 0042 Cursor Color 1 Blue 0043 Cursor Color 2 Red 0044...
Page 176 RAMDAC Register Contents Order Accessed Index Name 8 BPP 16 BPP 24 BPP 32 BPP 0088 MISR Blue 0089 - 008d Reserved 008E Pixel PLL VCO Divider Input 008F Pixel PLL Reference Divider Input 0090 VRAM Mask 0 0091 VRAM Mask 1 0092 VRAM Mask 2 0093...
Page 177 RAMDAC Synchronization This register controls how the RAMDAC uses the sync input signals and Control – Index 0x0003 how it drives the sync outputs. This register must contain 0x00. to operate correclty within its hardware environment. Horizontal Sync This register specifies the number of pixel clocks by which the horizontal Position –...
Page 178: Color Palette Accesses
RAMDAC 11.4.3 Color palette accesses The RAMDAC contains three 256 x 8 bit color lookup tables (palettes) which are accessed as a single 256 x 24 bit palette via an internal control mechanism. Before reading from the palette, the Palette Address (Read Mode) register must be written to specify the starting address.
Page 179: Pixel Formats
RAMDAC palette location in a single transfer. This mechanism allows successive byte writes to the Palette Data location to step through the 256 palette entries without the need to supply a new address for each access. The address register is reset to zero following an access to the blue color lookup entry at 0xFF.
Page 180 RAMDAC Display Interface 11-30...
Page 181: Chapter 12 Microcontroller Subsystem
Microcontroller Subsystem This chapter decribes the microcontroller subsystem which provides low-level system management for the SPARCbook 3. System management includes the following: • Monitoring and controlling initial system power-up • Handling keyboard and pointing stick input • Monitoring battery condition and charging •...
Page 182: Microcontroller Subsystem Overview
Microcontroller subsystem overview 12.1 Microcontroller subsystem overview The architecture of the microcontroller subsystem is illustrated in Figure 12-1. Real Time Serial Clock EEPROM D(0) D(1) D(7:0) µController A(15:0) Control Signals Pointing Stick Keyboard Microcontroller DUART Detection Scanning Card Thermal Management External Base Board Keyboard...
Page 183: Normal Operation
Microcontroller subsystem overview Assigning low level activites activities to a dedicated microcontroller in this way releives the main CPU of the burden of trivial activities, ensuring that it is employed effeciently running applications. The host CPU and microcontroller communicate via register locations within the TS102 address space.
Page 184: Internal Keyboard Scanning
Microcontroller subsystem overview 12.1.2 Internal keyboard scanning The microcontroller address bus signals are driven out to the internal keyboard drive lines and depressed keys are sensed via the data bus. The microcontroller implements debounce and key repeat control in software. 12.1.3 External keyboard and mouse The microcontroller subsystem incorporates a dual universal asynchronous receiver transmitter (DUART).
Page 185: Lcd Status Display
Microcontroller subsystem overview 12.1.7 LCD status display The status screen is managed by the microcontroller. The display can be programmed for continuous loop or static message display. A stringcode table defines characters and text strings to be used for any messages that the microcontroller generate’s to indicate, for example, that a low-power shutdown is imminent.
Page 186: Command Set
Command Set 12.2 Command Set The microcontroller command set is organized into several functional groups. The command structure is the same for all groups. 12.2.1 Command synchronization The administartion of the host-microcontroller link must be single threaded; only one data exchange may be active at any time. The sync command (0x00) can be used to bring the microntroller and host into phase.
Page 187 Command Set Opcode Command Argument Returned Function 0x0A Read ack + 4bytes This command returns the total number of seconds that the unit Power-on has been powered-on during its life. This value is held in Seconds EEPROM as a four byte value which are returned in order msb ... lsb.
Page 188 Read ack + 2 bytes This command returns the checksum of the microcontroller's Microntroller internal ROM. The checksum is calculated in the same way as the Tadpole EPROM Programmer and is returned in order Checksum msb…lsb. 0x10 Read Error ack + 2 bytes...
Page 189 Command Set Opcode Command Argument Returned Function 0x12 Read User ack + 2 bytes The User Conﬁguration Area of the EEPROM is used to store Conﬁguration long-lived system conﬁguration information. This area can be Area and read and written by using the read and write EEPROM Address commands, provided that the location of the record within the EEPROM can be ascertained.
Page 190 Command Set Opcode Command Argument Returned Function 0x1C Read Internal ack + 2 bytes This command returns the keyboard type (ﬁrst byte) and layout Keyboard information (second byte) for the unit's internal keyboard. This Layout value is recorded in EEPROM, but defaults to Sun Type 5 US layout if the EEPROM is corrupt.
Page 191: Read/Write/Modify Commands
Command Set 12.2.3 Read/Write/Modify Commands These commands are used to read or modify the byte attribute addressed. Each command uses the same form, where the value written to the attribute is given by: new_attribute = (old_attribute AND mask) EOR value The old attribute value is returned in all cases.
Page 192 Command Set Opcode Command Argument Returned Function 0x23 Speaker Volume mask ack + 1 byte The volume is controlled via a digital potentiometer which is varied with this command. Values in the range 0-255 (dec) are acceptable when setting this parameter.
Page 193 Command Set Opcode Command Argument Returned Function 0x2E Control Diagnostic mask ack + This command is used to control various features Mode ((mark_space_ratio used during diagnostic test of the system. By setting AND mask) EOR the appropriate bit in this simulated "port", a value) diagnostic feature is activated.
Page 194: Commands Returning No Status
Command Set 12.2.4 Commands Returning no Status The following commands are provided to simplify the use of the micromcontroller by system software, particularly form interrupt routines. No status is returned for these commands and in many cases the commands do not require arguments OpCode Command Argument...
Page 195: Block Transfer Commands
Command Set 12.2.5 Block Transfer Commands This gorup of commands handle transfers of arbitrary amounts of data, up to a maximum of 255 bytes, between the CPU and microcontroller. A length parameter of zero transfers no data. Attenpts to transfer excess data results in an error.
Page 196: Generic Commands
Command Set 12.2.6 Generic Commands This group of commands perform related functions and are of variable length. Opcode Command Argument Returned Function 0x50 Deﬁne Key (sequence and The built-in keyboard features an 86-key pad. Combination Entry combination_length Normal Sun 4 type 5 keyboards offer up to 106 keys, including a separate numeric keypad, some of which must be simulated with key-combinations.
Page 197: Generic Commands With Optional Status
Command Set Opcode Command Argument Returned Function 0x52 Deﬁne Status length <message The LCD status screen can be set up to display a Screen Display bytes and puase continuous loop of messages separated by descriptor> deﬁnable pauses, or to display a single message. All messages must be predeﬁned entries in the string table, identiﬁed by their index number.
Page 198: Administration Commands
Command Set 12.2.8 Administration Commands Opcode Command Arguments Returned Function 0x70 Set User Password length <password> The supplied user password is encrypted and stored in EEPROM. The microcontroller fails attempts to use this command if a password not been supplied when required.
Page 199: Appendix A Further Information
Further Information This appendix provides a list of publications or websites to which you can refer for further information about components used in the SPARCbook 3.
Page 200: Further Information
Device Facility Provided Contact STSX1012 microSPARC II CPU, SBus controller, memory controller http://www.sun.com/sparc TurboSPARC Microprocessor User’s Guide Revision 1.0, October 1996 CPU, SBus controller, memory controller TurboSPARC Fujitsu Microelectronic Inc., 3545 North First (S3TX only) Street, San José CA 95134-1804 http://www.fujitsumicro.com NCR89C100 MACIO Ethernet, SCSI, Parallel...
Page 201: Appendix B Connector Information
Connector Information This appendix provides a pinouts for the connectors used the SPARCbook 3.
Page 202: Dcin
I/O Panel Connectors I/O Panel Connectors This chapter provides details of the connector-pin signal assignments for the interfaces on the I/O panel. SPARCbook 3 systems are supplied with cable adapters, where required, so that interfaces appear on the appropriate industry standard connector. Note SPARCbook 3 Connections between the...
Page 203: Parallel (S3 And S3Lc
I/O Panel Connectors B.1.3 Parallel (S3 and S3LC) The following connector is ﬁtted on the I/O panel of the S3 and S3LC models. Connector Signal Signal Signal Ground SELECT_IN /STROBE Signal Ground Signal Ground DATA(0) DATA(1) DATA(2) +5 V Signal Ground Signal Ground DATA(4) DATA(3)
Page 204: Ethernet (S3 And S3Lc
I/O Panel Connectors B.1.5 Ethernet (S3 and S3LC) The following connector is ﬁtted on the I/O panel of the S3 and S3LC models. It is also present on a cable adapter supplied with the S3XP, S3GX and S3TX models. Connector Signal Signal Chassis Ground...
Page 205: Scsi (S3Xp, S3Gx And S3Tx
I/O Panel Connectors B.1.7 SCSI (S3XP, S3GX and S3TX) The following connector is ﬁtted on the I/O panel of S3 XP, S3GX and S3TX and is present on the a cable adapter supplied with S3 and S3LC Connector Signal Signal Signal Ground SCSI D (0) Signal Ground...
Page 206: Scsi (S3 And S3Lc
I/O Panel Connectors B.1.8 SCSI (S3 and S3LC) The following connector is ﬁtted to the I/O panel of S3 and S3LC models. Connector Signal Signal Not connected SCSI D(6) SCSI D(0) Signal Ground Signal Ground SCSI D(7 SCSI D(1) SCSI D(PARITY) SCSITERMPWR Signal Ground SCSI D(2)
Page 207: Isdn
I/O Panel Connectors B.1.11 ISDN The following connector is not present on the S3LC. Connector Signal Signal Not Connected TE IN– 2 3 4 5 Not Connected TE OUT– TE OUT+ Not Connected TE IN+ Not Connected Modem Connector Signal Signal Not Connected 2 3 4 5...
Page 208: Cable Adapter Connectors
Cable Adapter Connectors Cable Adapter Connectors B.2.1 Parallel Cable Adapter The following connector is ﬁtted on the parallel cable adapter supplied with all SPARCbook 3 models. Connector Signal Signal /STROBE /AUTOFEED DATA (0) /ERROR DATA (l) /INIT DATA (2) /SELECT_IN DATA (3) Signal Ground DATA (4)
Page 209: B.3 Removable Hard Drive Scsi Connector
Removable Hard Drive SCSI Connector Removable Hard Drive SCSI Connector Signal Signal MOTORVCC MOTORVCC MOTORGND MOTORGND /SCSIIO /SCSICD SCSID(7) /SCSISEL /SCSIREQ SCSID(6) /SCSIRST /SCSIMSG SCSID(5) /SCSIIACK /SCSIATN SCSID(4) /SCSIBSY SCSID(3) /SCSITPWR SCSID(2) /SCSID(P) NOT CONNECTED SCSID(1) NOT CONNECTED /MOTOROFF SCSID(0) MOTORVCC MOTORVCC Connector Information...
Page 210: Removable Hard Drive Scsi Connector
Removable Hard Drive SCSI Connector Connector Information B-10...
Page 211 Index Numerics 16-bit Audio interface 8-1 Cache Controller and MMU 2-8 card interrupt registers, PCMCIA 7-8 card status registers, PCMCIA 7-9 class 2 fax command set 9-27 address map clock, SCC 4-10 Power 9100 registers 11-8 color palette accesses 11-28 SLAVIO 3-4 command register, SCSI 5-3 TS102 7-4...
Page 212 DMA support 6-5 Ethernet controller 1-11 data mode, audio CODEC 8-20 control and status register 0 6-3 DBRI control and status register 1 and 2 6-4 command summary 8-12 control and status register 3 6-5 commands 8-11 FIFOs 6-2 internal registers 8-7 Ethernet descriptor management 6-2 programming model 8-4 Ethernet interface 6-1...
Page 213 RAMDAC 11-23 linked lists, ISDN 8-6 instruction set overview 2-3 logic states, definition xi integer unit 2-5, 2-6 control registers 2-6 cycles per instruction 2-4 MACIO 1-10 window registers 2-6 address space 3-2 integer unit, microSPARC 2-3 diagnostic message register 3-10 internal keyboard scanning 12-4 LED/Floppy (Aux1) Register 3-11 internal modem 9-1, 9-27...
Page 214 network power down register, MACIO 3-12 interface architecture 6-1 Power9100 note on P9100 register access 11-9 configuration registers 11-7 note on RAMDAC access delays 11-22 processor 1-5 note on RAMDAC address autoincrement 11-23 programming model, DBRI 8-4 page table pointer 2-11 RAM, battery backed 1-13 parallel connector B-5 RAMDAC 11-21...
Page 215 connecting devices 5-2 Power 9100 11-8 SCSI controller 1-10, 5-1 status registers, SCSI 5-5 configuration registers 5-6 SVGA unit 11-7 DMA registers 5-7 synchronization, display 11-4 DMA support 5-7 synchronous transfer period register, SCSI 5-6 FIFO/flags register 5-6 system architecture 1-1 interrupt status register 5-5 system bus architecture 1-6 interrupts 5-7...
Page 216 Index-vi...

Tadpole SPARCbook 3 series Reference Manual

About this Guide

Chapter 1 Architecture Overview

Chapter 2 The SPARC CPU

Chapter 3 Memory Map and Interrupts

Chapter 4 Serial Interface

Chapter 5 SCSI Controller

Chapter 6 Ethernet Interface

Chapter 7 PCMCIA Interface

Chapter 8 ISDN and 16-Bit Audio

Chapter 9 MODEM

Chapter 10 Parallel Interface

Chapter 11 Display Interface

Chapter 12 Microcontroller Subsystem

Appendix A Further Information

Appendix B Connector Information

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Summary of Contents for Tadpole SPARCbook 3 series

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