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Philips Semiconductors
12-bit high-speed Analog-to-Digital
Converter (ADC)
SYMBOL
Voltage controlled regulator input V
V
full scale fixed voltage
ref(FS)
V
V
input voltage amplitude
i(p-p)
i(p-p)
(peak-to-peak value)
I
input current at V
ref
Outputs (referenced to DGND)
D
D11
IGITAL OUTPUTS
TO
V
LOW-level output voltage
OL
V
HIGH-level output voltage
OH
I
output current in 3-state
O
Switching characteristics
C
f
LOCK FREQUENCY
clk
f
minimum clock frequency
clk(min)
f
maximum clock frequency
clk(max)
TDA8767H/1
TDA8767H/2
TDA8767H/3
t
clock pulse width HIGH
CPH
t
clock pulse width LOW
CPL
Analog signal processing; 50% clock duty factor; V
L
INEARITY
ILE
integral non-linearity
DLE
differential non-linearity
OFER
offset error
GER
gain error amplitude; spread
from device to device
B
(f
= 30 MHz); note 1
ANDWIDTH
clk
B
analog bandwidth
t
analog input settling time
STLH
LOW-to-HIGH transition
t
analog input settling time
STHL
HICH-to-LOW transition
H
ARMONICS
THD
total harmonic distortion
1999 Feb 16
PARAMETER
(referenced to V
ref
ref
D0
IR (
AND
REFERENCED TO
(see Fig.3)
CONDITIONS
)
CCA
V
= 5 V
CCA
differential mode
single mode; V
= 2.5 V
i
DGND)
I
= 2 mA
OL
I
= 0.4 mA
OH
0.5 V < V
< V
O
CCO
SH = HIGH
SH = LOW
V
= 2.0 V; V
i
i
f
= 4 MHz; ramp input
clk
f
= 4 MHz; ramp input;
clk
no missing codes
V
= V
= V
= 5 V;
CCA
CCD
CCO
T
= 25 C; V
= V
; output
amb
i
i
code = 2047
V
= V
= V
= 5 V;
CCA
CCD
CCO
T
= 25 C; V
V
= 2.0 V
amb
i
i
1 dB
3 dB
full scale square wave;
note 3
full scale square wave;
note 3
f
= 30 MHz; f
= 4.43 MHz;
clk
i
note 2
8
Preliminary specification
MIN.
TYP.
3.175
2.0
2.0
10
0
V
0.5
CCO
20
10
20
30
8.5
8.5
= V
2 V; see Table 1
ref
CCA
3.0
0.6
tbf
tbf
9
18
tbf
tbf
64
TDA8767
MAX.
UNIT
V
V
V
A
0.5
V
V
V
CCD
+20
A
1
MHz
1
kHz
MHz
MHz
MHz
ns
ns
4.0
LSB
1
LSB
tbf
LSB
tbf
LSB
MHz
MHz
ns
ns
dB
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