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Philips Semiconductors
12-bit high-speed Analog-to-Digital
Converter (ADC)
APPLICATION INFORMATION
handbook, full pagewidth
220 nF
1 : 1
IN
100
4.7 F
The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 s or a pull-up resistor must be connected between CLK and V
(2) R1, and R2 must be determined in order to obtain a middle voltage of 2.5 V; see Table 1. To ensure a sufficient analog input stability, the minimum
current into these resistors must be about 1 mA.
(3) V
must be decoupled to V
ref
1999 Feb 16
V I
V I
100
V CCA
R1
5 V
100 nF
(2)
10
R2
nF
100 nF
5 V
(3)
100 nF
V ref
MBH145
.
CCA
Fig.6 Application diagram (differential input mode).
5 V
SH
mode
100 nF
44 43 42 41 40 39 38 37 36 35 34
n.c.
1
2
3
4
n.c.
5
TDA8767H
n.c.
6
n.c.
7
n.c.
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
n.c.
n.c.
n.c.
n.c.
5 V
100 nF
13
Preliminary specification
5 V
100 nF
(1)
CLK
n.c.
5 V
100 nF
33
32
D0 (LSB)
D1
31
30
D2
29
D3
28
D4
27
D5
26
D6
25
D7
24
D8
D9
23
IR
D10
D11
(MSB)
chip select input (OE)
output format select (TC)
TDA8767
.
CCD
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