iSystem Target Board LPC2138 User Manual

Philips/nxp target board user's guide

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User's Guide
© iSYSTEM, March 2007
Philips/NXP LPC2138 Target Board
Ordering code
Dimensions
Figure 1: ITLPC2138FE Target Board
ITLPC2138
100 x 96 mm
V1.7
1/13

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Summary of Contents for iSystem Target Board LPC2138

  • Page 1 User’s Guide Ordering code Dimensions © iSYSTEM, March 2007 Philips/NXP LPC2138 Target Board ITLPC2138 100 x 96 mm Figure 1: ITLPC2138FE Target Board V1.7 1/13...
  • Page 2: Table Of Contents

    Contents Contents... 2 Introduction ... 3 Description ... 3 View of the ITLPC2138 ... 3 Block Diagram ... 4 Components List ... 5 Power Supply... 5 Jumper & Connector Descriptions... 6 Connectors... 7 Schematic ... 10 Use of the on-board integrated debugger ... 11 Use of an external debugger...
  • Page 3: Introduction

    Introduction NXP LPC2138 Target Board is an evaluation and a development system for NXP ARM7TDMI-S based LPC2138 microcontroller. The ITLPC2138 package consists of a USB cable and a target board populated with NXP LPC2138 CPU, minimum peripherals, JTAG debug connector, ETM trace connector and an on-board integrated iSYSTEM debugger.
  • Page 4: Block Diagram

    Block Diagram Figure 3: ITLPC2138 Block diagram Notes 1. The board provides 16-pin connector for the optional LCD display (type CMC216x04 or EW162B0GLY, checkout backlight LED polarity), which is not included in the package. © iSYSTEM, March 2007 4/13...
  • Page 5: Components List

    Components List Name J1, J2, J7 - J10, J15 - J20, J22,J25 LD0 – LD3 LD11 LD12 T0 – T3 Reset (T4) R25, R26 *See schematic for details. Power Supply The target board is powered from the PC USB port, through which winIDEA (IDE) running on a PC, connects to the on-board integrated debugger.
  • Page 6: Jumper & Connector Descriptions

    Jumper & Connector Descriptions • J1, J2: LCD LED Backlight Polarity: If J1 and J2 is set in position 1-2, then LCD pin15 is connected to +5V and pin16 is connected to GND. If J1 and J2 is set in position 2-3 then pin15 is connected to GND and pin16 is connected to +5V.
  • Page 7: Connectors

    Connectors DB9 male connector UART1 (P35) The serial port is configured as a standard RS232 interface with RTS/CTS control. Cross female to female cable is needed for connection with PC computer COM port. 16-pin LCD connector (P21) Pin Assignment for Crystal Clear technology CMC216x04 or EDT EW162B0GLY LCD Pin No.
  • Page 8 20-pin JTAG Debug Connector (P33) An external JTAG debug tool can be connected to a 20-pin P33 debug connector. Jumper J9 must be set to 2-3 position when using an external debugger. 38-pin Mictor JTAG Debug & ETM Trace Connector (P32) Not used Not used Not used...
  • Page 9 CPU expansion connectors Figure 4: Expansion connectors All CPU signals are available on the expansion connectors, which are standard connectors with a 2.54 mm raster. © iSYSTEM, March 2007 9/13...
  • Page 10: Schematic

    Schematic Note: On-board integrated debugger is not part of the schematic. © iSYSTEM, March 2007 10/13...
  • Page 11: Use Of The On-Board Integrated Debugger

    Use of the on-board integrated debugger Follow below instructions, in order to get a sample application running with “out of the box” experience. All jumpers are set in the default position during the final tests in the manufacturing. If winIDEA 2006 CD is not part of the package, please obtain winIDEA 2006 setup from your local iSYSTEM office or from www.isystem.com.
  • Page 12: Use Of An External Debugger

    Use of an external debugger An external debugger can be: • a JTAG debugger, which connects to a 20-pin P33 connector • a development tool supporting JTAG debugging and ETM (on-chip trace), which connects to a 38-pin Mictor P32 connector Setting up a debug environment for the first time •...
  • Page 13: Troubleshooting

    Troubleshooting The flash boot loader code is executed every time the CPU is powered or reset. The loader can execute the ISP command handler or the user application code. P0.14 is sensed on a rising edge on the RST (CPU reset) pin. If a low level is detected, ISP command handler starts and takes over control of the CPU after reset.

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