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Philips Semiconductors
6. Hardware description
6.1.
Block diagram
Figure 6-1 shows the block diagram of the ISP1301 evaluation board.
PC PARALLEL-TO-I
PARALLEL
CONVERTER
PCF8584 I
ISA
CONTROLLER
HC, DC and OTG CORE
LOGIC INTERFACE
FPGA
CONNECTOR
INTERFACE
(to the ISP1362 FPGA or
Phone FPGA)
6.2.
Functional description
A brief description of each function module is given in the following sections.
6.2.1.
PCF8584 I
This block provides functions of the I
ISP1362 or ISP1161x ISA interface board, or any other generic 8-bit microprocessor interface through a 40-wire
IDE cable. The PC or other microprocessor can service the interrupt from the ISP1301 and access the registers of
the ISP1301 through this interface.
6.2.2.
PC parallel to I
This interface provides an alternative method to access the ISP1301 I
emulate software I
6.2.3.
HC, DC and OTG core logic interface connector
This interface provides connection to a Host Controller (HC), Device Controller (DC) or On-The-Go (OTG)
core logic. This interface is used during OTG system-level evaluation or during compliance testing.
UM10028_1
User's Guide
2
C
2
C-BUS
CORE INTERFACE (OE, VP, VM, RCV,
SPEED, SUSPEND, RESET, V
Figure 6-1: Block diagram of the ISP1301 evaluation board
2
C-bus controller
2
C-bus to the 8-bit parallel-bus converter. It can connect to the Philips
2
C converter
2
C master to access the ISP1301 I
Rev. 1.0—February 2003
ISP1301 USB OTG Transceiver Eval Kit User's Guide
4-PIN I
2
C
HEADER
ISP1301
OTG TRANSCEIVER
)
DD_LGC
2
C interface through the PC. The PC needs to
2
C slave.
AUDIO INTERFACE
(L/R SPEAKER LINE IN,
MIC PRE-AMP OUT)
DP, DM, ID, V
BUS
V
POW ER MANAGER
BAT
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
m ini-AB Receptacle
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