Faultfinding Guide - Philips CDR570 Service Manual

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Faultfinding Guide

8. Faultfinding Guide
8.1 Display Board
8.1.1 Description of display board
General description
The display board has three major parts : the FTD (Fluorescent
Tube Display), the display controller TMP87C874F and the
keyboard. The display controller is controlled by the DASP
master processor on the CDR main board. The communication
protocol used is I2C. So all the information between DASP and
display controller goes via the SDA or I2C DATA and SCL or
I2C CLK lines. Communication is always initiated by the DASP
on the CDR main board. Unlike the previous generations of
CDR players, the interrupt generated by the display controller
at key-press or reception of remote control is not used. Instead,
the DASP polls the display controller for these events.
PIN DESCRIPTIONS
BLOCK DIAGRAM
TMP87C874F
64 63 62 61 60 59 58
I/O PORT8 (VFT)
65
66
67
DATA MEMORY
68
( RAM )
512X8 BIT
69
70
71
72
73
16 BIT
74 TIMER/COUNTER
75
76
8 BIT A/D
77
CONVERT.
78
VKK
79
80
I/O PORT0
1 2 3 4 5 6 7
INT0 external interrupt input 0
INT1 external interrupt input 1
RESETN reset signal input, active low
SCL I2C-bus serial clock input/output
SDA I2C-bus serial data input/output
TEST test pin, tied to low
VAREF analog reference voltage input
VASS analog reference ground
VDD +5V
VKK VFT driver power supply
VSS ground
XIN, XOUT resonator connecting pins for high-frequency clock
Display controller TMP87C874F
TMP87C874F (IC7104) is a high speed and high performance
8-bit single chip microprocessor, containing 8-bit A/D
conversion inputs and a VFT (Vacuum Fluorescent Tube)
driver. In this application, its functions are :
•
•
•
•
•
•
All the communication runs via the serial bus interface I2C. The
display controller uses an 8Mhz resonator as clock driver.
57 56 55 54 53 52 51 50 49
I/O PORT7 (VFT)
PROGR MEMORY
( ROM )
8kX8 BIT
C P U
INTERRUPT
CONTROLLER
CLOCK/TIMING CONTROLLER
( I/O PORT2 )
8 9 1 5 1 6 10 11 12 1 9 13 14
Figure 8-9
CDR570/930
slave microprocessor.
FTD driver.
generates the square wave for the filament voltage
required for an AC FTD.
generates the grid and segment scanning for the FTD.
generates the scanning grid for the key matrix.
input for remote control.
48 47 46 45 44 43 42 41
I/O PORT6 (VFT)
VDD
VAREF
VASS
PROGRAM
COUNTER
8 BIT
TIMER/COUNTER
I/O PORT1
I C 2
PORT3
17 18 20 21 22 23 24
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