Faultfinding Guide - Philips CDR779 Service Manual

8. Faultfinding Guide

8.1 Display Board
8.1.1 Description of display board
General description
The display board has three major parts : the FTD
(Fluorescent Tube Display), the display controller
TMP87C874F and the keyboard. The display controller is
controlled by the DASP master processor on the CDR main
board. The communication protocol used is I2C. So all the
information between DASP and display controller goes via
the SDA or I2C DATA and SCL or I2C CLK lines.
Communication is always initiated by the DASP on the CDR
main board. Unlike the previous generations of CDR players,
the interrupt generated by the display controller at key-press
or reception of remote control is not used. Instead, the DASP
polls the display controller for these events.
BLOCK DIAGRAM
TMP87C874F
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN DESCRIPTIONS
INT0
INT1
RESETN
SCL
SDA
TEST
VAREF
VASS
VDD
VKK
VSS
XIN, XOUT
64 63 62 61 60 59 58 57 56
I/O PORT8 (VFT)
DATA MEMORY
( RAM )
512X8 BIT
16 BIT
TIMER/COUNTER
8 BIT A/D
CONVERT.
VKK
I/O PORT0
1 2 3 4 5 6 7 8 9 1 5 1 6
external interrupt input 0
external interrupt input 1
reset signal input, active low
I2C-bus serial clock input/output
I2C-bus serial data input/output
test pin, tied to low
analog reference voltage input
analog reference ground
+5V
VFT driver power supply
ground
resonator connecting pins for high-frequency clock
Faultfinding Guide
Display controller TMP87C874F
TMP87C874F (IC7104) is a high speed and high
performance 8-bit single chip microprocessor, containing 8-
bit A/D conversion inputs and a VFT (Vacuum Fluorescent
Tube) driver. In this application, its functions are :
• slave microprocessor.
• FTD driver.
• generates the square wave for the filament voltage
required for an AC FTD.
• generates the grid and segment scanning for the FTD.
• generates the scanning grid for the key matrix.
• input for remote control.
All the communication runs via the serial bus interface I2C.
The display controller uses an 8MHz resonator as clock
driver.
55 54 53 52 51 50 49 48 47
I/O PORT7 (VFT)
PROGR MEMORY
PROGRAM
( ROM )
COUNTER
8kX8 BIT
C P U
INTERRUPT 8 BIT
CONTROLLER TIMER/COUNTER
CLOCK/TIMING CONTROLLER
( I/O PORT2 )
I/O PORT1
10 11 12 1 9 13 14 17 18
Figure 8-1
CDR779
46 45 44 43 42 41
I/O PORT6 (VFT)
40
VDD
39
VAREF
38
VASS
37
36
35
34
33
32
31
30
29
28
27
26
25
I C 2
PORT3
20 21 22 23 24
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