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5-7. TIMER/TUNER CONTROL MICROPROCESSOR PIN FUNCTION (FR-137 BOARD IC301)
Pin No.
Pin Name
I/O
1
N.C
–
Not used (UNSW 5V)
2
POWER FAIL
I
Power failure detect signal input
3
N.C
–
Not used (UNSW 5V)
4
SIRCS IN
I
Remote control signal (SIRCS) input
5
STEREO DET
I
STEREO detect signal
6
N.C
–
Not used
7
BUZZER
O
Buzzer signal output
8
N.C
–
Not used
9
N.C
–
Not used
10
SCK 0
I
Serial communication signal (Serial clock)
11
SI 0
I
Serial communication signal (Data input)
12
SO 0
O
Serial communication signal (Data output)
13
SAP DET
I
SAP detect signal (Not used)
14
LANC IN
I
LANC signal input
15
LANC OUT
O
LANC signal output
16
A/D 0
I
Analog voltage (KEY) input
17
A/D 1
I
Analog voltage (KEY) input
18
A/D 2
I
Analog voltage (KEY) input
19
F MONO
O
F MONO signal
20
AFT
I
AFT (Auto fine tuning signal input)
T E
L 1 3 9 4 2 2 9 6 5 1 3
21
H DET
I
H DET (TUNER H SYNC detect input)
22
A/D 6
I
Analog voltage (KEY) input
23
A/D 7
I
Analog voltage (KEY) input
24
AVDD
–
UNSW 5V
25
AV REF
I
A/D port reference input UNSW 5V
26
SCL 0
O
T BUS (clock)/IIC BUS (clock)
27
CG CS
O
Character generator chip select signal
28
SDA 0
O
IIC BUS (data)
29
LED CS
O
LED driver chip select signal
30
AVSS
–
Ground
31
EXTAL
O
System clock terminal (16MHz)
32
XTAL
I
System clock terminal (16MHz)
33
VSS
–
Ground
34
RST
I
RESET signal input
35
PLL CLK
O
TUNER PLL clock
36
PLL DATA
O
TUNER PLL data
37
PLL ENABLE
O
TUNER chip select
38
MAIN/SAP
O
MAIN/SAP select signal
39
N. C
–
Not used
40
TA MUTE
O
TUNER audio mute signal output
41
DMS 2
I
DMS fowared/reverse signal input
42
DMS 1
I
DMS fowared/reverse signal input
43
VFDP
–
VFDP
www
44
SEG1
O
Segment terminal 1
45
SEG2
O
Segment terminal 2
46
SEG3
O
Segment terminal 3
47
SEG4
O
Segment terminal 4
.
48
SEG5
O
Segment terminal 5
49
SEG6
O
Segment terminal 6
50
SEG7
O
Segment terminal 7
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Function
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8
9
Pin No.
Pin Name
I/O
51
SEG8
O
Segment terminal 8
52
SEG9
O
Segment terminal 9
53
SEG10
O
Segment terminal 10
54
SEG11
O
Segment terminal 11
55
SEG12
O
Segment terminal 12
56
SEG13
O
Segment terminal 13
57
SEG14
O
Segment terminal 14
58
SEG15
O
Segment terminal 15
59
SEG16
O
Segment terminal 16
60
N.C
–
Not used
61
N.C
–
Not used
62
N.C
–
Not used
63
N.C
–
Not used
64
N.C
–
Not used
65
N.C
–
Not used
66
GRID6
O
Grid terminal 6
67
GRID5
O
Grid terminal 5
68
GRID4
O
Grid terminal 4
69
GRID3
O
Grid terminal 3
70
GRID2
O
Grid terminal 2
Q
Q
3
7
6
3
1
5
1
71
GRID1
O
Grid terminal 1
72
VDD
–
UNSW5V
73
TX
I
Timer clock terminal (32KHz)
74
TEX
O
Timer clock terminal (32KHz)
75
NC/VPP
–
UNSW5V
76
ASURA CS
O
S/S microcomputer chip signal
77
ASURA RESET
O
System reset output
78
WC
O
EEP ROM WRITE Control Signal
79
POWER CONT
O
Power supply control signal
80
CG V
I
Composite sync input
c o
.
2
4
2
9
8
Function
5
0
8
9
2
4
9
8
2
m
9
9
9
9
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