Philips DVDR3355 Service Manual page 66

EN 66 8. 3139 785 30981
PIN DESCRIPTION
TERMINAL
TYPE TYPE
NAME PHP NO.
AGND 26, 32, 36 Supply
AV DD 25, 35 Supply
C/LKON 15 CMOS
CNA N/A CMOS
CPS 20 CMOS
CTL0 2 CMOS
CTL1 3
D0 4 CMOS
D1 5
D2 6
D3 7
D4 8
D5 9
D6 10
D7 11
Circuit- and IC Description
I/O I/O
– Analog circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
– Analog circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001
μF. Lower frequency 10 μF filtering capacitors are also recommended. These
supply terminals are separated from PLLV DD and DV DD inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.
I/O Bus manager contender programming input and link-on output. On hardware reset,
this terminal is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-kΩ series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI
(cable-power-status interrupt), or STOI (state-time-out
interrupt) register bits are 1 and the RPIE (resuming-port
interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.
O Cable-not-active output. This terminal is asserted high when there is no incoming
bias voltage.
I Cable power status input. This terminal is normally connected to cable power
through a 400-kΩ resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DV DD
supply if application does not require it to be used.
I/O Control I/Os. These bidirectional signals control communication between the
TSB41AB1 and the LLC. Bus holders are built into these terminals.
I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the
LLC. Bus holders are built into these terminals.
DESCRIPTION DESCRIPTION