Yamaha YSP-800 Service Manual page 59

A B C
SCHEMATIC DIAGRAM (INPUT 1/2)
1
L 5.4 5.8 5.8
1
5.8 5.8
5.8
5
0
2
0
VCR 6.4 6.4
4
8.3 8.4
INPUT
R
SELECTOR
AUDIO
5.8 5.8
INPUT
12
5.4 5.4
5.8 5.8
14
L 6.4 0
15
6.4 0
2 8.4
8.4
TV/STB
R
SUBWOOFER
OUT 0
3
VIDEO
14 5.0
2.6
DVD 5
3.2 6 0
COAXIAL 9 8
7 0
DIGITAL
INPUT
4.4
4
0
TV/STB
5.0
OPTICAL
4.4
0
AUX
5.0
5.0
0
4.4
13 12 1 2
4.4 0 5.0
11 10 3 4
to RS-232C
Conversion Jig
5
SYSTEM
CONNECTOR
(U, C, J models)
6
7
-22.6
-16.2
-16.2
-20.9
-22.6
-22.6
-17.8
-17.8
-19.4
-16.2
FL DRIVER
-19.4
-17.8
8
9
IC1: TC74HCU04AFEL IC2, 801: NJM2068MD-TE2
Hex Inverters Dual OP-Amp
1A 1 14 VCC
1
OUT 1 8 +V CC
1Y 2 6A
13
–IN 2 7 OUT
1 2
+ – + –
2A 3 12 6Y
+IN 1 3 6 –IN 2
2Y 4 11 5A
–V 4 5 +IN
CC 2
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y
10
D E F
5.8
5.8
3 5.8
0
0
0
5.8
5.8
13 5.8
0
AMP
11.7
11.7 6
7 0
8 11.1
5
5.6
5.6 2
1 0
0
4 3
0
3.3
M62782GP
4.9 4.9
4.9
3.2 4.9 5.0
4.9
0
0
0 0
4.9 4.9
0 11
1.8 0
0 2.5
1.7
4.9 0
OSD
0 0
0
3
0 0
0 A-1 0
4.9 0
6
2.8
0
8
1.8
0
5.0 6.9
6.9
5.0
INPUT(2)
FL DISPLAY
-22.4
-22.6
-16.1
-16.1
-16.2
-16.2
-16.2
-14.6
3.4
1.6
1.6
0
3.2
3.2
3.2
3.2
INPUT(3)
IC5: µPC4570G2
IC4: TC4052BF
Analog Multiplexers/Demultiplexers Dual OP-Amp
VDD
16
OUT 1
1
13 X-COMMON
–IN 2
1
12 + – + –
I/O c O/I 0X
+IN 1 3
I/O c O/I 14 1X
A 10
15 2X
I/O c O/I –V 4
CC
11
I/O c O/I 3X
9
B
I/O c O/I 1 0Y
5 1Y
I/O c O/I
6
INH
I/O c O/I 2 2Y
I/O c O/I 4 3Y
3 Y-COMMON
8 7
VSS VEE
G H
0
14
0 13
0 14
7
0 1
Page 60 J4
0 2
to INPUT(1)_CB505
0 4
5
0
0 9
10K 10K
0
10
RF45710 RF45710
10K
RF45710
W801 8 11.1
5.1
5.1
5 5.1
7 5.1
1.4
6
5.1
Page 57 J4
to DSP_CB8
FRONT SW
INPUT(4)
IR-IN
IC9: M62782GP
Voltage Threshold Detector
SUPPLY VOLTAGE
4
R1
OSC
-
+ COUNTER
R2
1.25V
3 2 1
N.C. SUB GND
(GND)
IC6: MAX3232CDWR IC7: TC74HCT08AF IC10: NJM78M05FA
3-V TO 5.5-V MULTICHANNEL Quad 2-Input And Gate Voltage Regulator
RS-232 LINE DRIVER/RECEIVER
1A 1 14 Vcc
8 +V
CC
1B 2 13 4B
OUT
7 2 C1+ 1 16 VCC 1Y 3 12 4A
V+ 2 15 GND 2A 4 11 4Y
6 –IN 2
2B 5 10 3B
C1 3 14 DOUT1
5 +IN
2
2Y 6 9 3A
C2+ 4 13 RIN1
GND 7 8 3Y
5 12
C2 ROUT1
6 11
V DIN1
DOUT2 7 10 DIN2
8 9
RIN2 ROUT2
I J K
POINT A-1 pin 6 of IC8
10K 10K
RF45710 RF45710
IC901: M66003-0101FP
FL Display Driver
/CEFL 2 Serial
CKFL 3 receive
circuit
DTFL 4
XIN 7
Clock
generator
XOUT 6
4.8
1.4 3
1 6.6
4 0 2
/RESET 1
VDD 8
Vcc2 18
Vss 5
Vp 64
INPUT(5)
IC8: MB90050PF
On-Screen Display Controller
SIN
Serial input
Each block
SCLK
control
CS
VIN
YIN
CIN
HSYNCI
VSYNCI Sync control
Video signal
FLDI generator circuit
SYNCST
HSYNCO
VSYNCO Output control
NTSC/PAL
signal
CSYNCO
generator
FLDO Pallete
circuit
(4 bits→6 bits)
VBLKO
Display Memmory control
BUSY
5 OUTPUT
GND 1
5 OUTPUT VRAM
SUB 2 Font RAM
Font ROM
(GND) (35 characters
SUPPLY × 16 lines) (512 characters)
3 4
N.C.
VOLTAGE
EXS
4FSC clock
oscillation Each block
XS
circuit
FSC4O
EXD
Dot clock
XD oscillation Each block
circuit
DCLKO
INPUT
All reset
RESET
OUTPUT
COMMON
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
L M N
YSP-800
Display code
RAM CGROM
P35
(35 bit x 166) 44
(8-bit x 60)
Segment P10
19
Code
output
write P9
17
circuit
CGROM P1
dot data 9
data (35 bit x 16)
write
Code/
command
45 P36
control
circuit
52 G12
G13
51
code Segment
50 G14
select
digit
select/
49
output
timing Display
clock controller scan pulse circuit
48
P38
47
46 P37
63 G1
Digit
output
circuit
53 G11
VOUT
Analog
switch YOUT
COUT
FLDI 1 36 PO3
VSYNCI 2 35 PO2
HSYNCI 3 34 DCOL5
DCOL5 to DCOL0
VCC 4 33 DCOL4
DB
VSS 5 32 DCOL3
MB90050
DH
EXS 6 31 DCOL2
XS 7 30 DCOL1
FSC4O 8 29 DCOL0
VSYNCO 9 28 DCLKO
HSYNCO 10 27 DB
CSYNCO 11 26 DH
(8 characters)
VBLKO 12 25 RESET
PO3
PO2
Port control
PO1
PO0
59