Yamaha YSP-800 Service Manual page 57

A B C
SCHEMATIC DIAGRAM (DSP 3/3)
1
2
3
0
4
3.3
3.2
3.1
2.6
3.3
3.2
1.7
1.7
0.7
0
0
0
1.7
0.9
1.7
1.7
2.5
5
6
0
3.3
7 3.2
3.1
2.6
3.3
3.2
1.7
1.7
0.7
0
0
0
0
0.9
1.7
1.7
2.5
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
D E F
2.5
3.2
3.3
0
0
3.2
3.2
0
3.3 0
1.7 0
0
1.7
0
0
1.6
3.0
0.7 3.2
1.5 3.2
1.5 3.4
1.5 0
1.5 0
1.5
1.5 3.2
0
0 0.4
0 0
0
3.3 0
EEPROM
2.5
3.3
1.7
1.7
1.5
1.5
1.5
1.5
1.5
0
3.3
1.7
0 0
1.7 0
3.2
1.7
0
0 3.3
3.3 4.8
0
0 2.4
5.0 2.4
DAC
SW
G H I
3.3 3.3
0
2
B-1
0
1
3.2
3.2
3.3
A-3
0.1
0
3.3
3.3
3.3
0
3.3
3.3
3.0
MPU
0
0
0
0
0
0
0
3.2
3.2
1.7
1.6
0
1.7 0
1.7 3.2
0
0 3.3
3.3 4.1
2.0 0
0 2.1
5.0 2.1
DSP
POINT A-3 pin 13 of IC24
J K L
IC18, 19: YSS930-SZ
DSP
MICROPROCESSOR
INTERFACE
PROGRAM COEFFICIENT ADDRESS
RAM RAM
CONTROL REGISTER 50 bit ＊1024 word 16 bit ＊1024 word 17 bit ＊256 word
CONTROL
SIGNALS
SDBCK
SDWCK
SDI0
SDI1
SDI2
SDI3
32 bit DSP Core
SDI4
SDI5
SDI6
SDI7
DSP INTERNAL
OPERATING CLOCK
CK (30.72~40.96MHz)
EXTERNAL RAM
INTERFACE
PLL
IC20, 22: WM8728
24bit, 192kHz Stereo DAC
MODE LATI2S SCKDSD SDIDEM MUTEB CSBIWL
16 20 19 18 17 15
BCKIN
3
LRCIN 1
DIN 2
4 10 7
MCLK AVDD DVDD
IC21: S-29630AFJA
CMOS SERIAL EEPROM
Address
Memory array
decoder
Data register Output buffer
DI
Mode decode logic
CS
SK
Clock generator
M N
YSP-800
RAM
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
ZERO
5
VOUTR
8
11 VOUTL
12 VMID
14 13 9 6
VREFP VREFN AGND DGND
CS 1 8 VCC
VCC
SK 2 7 NC
GND
DI 3 6 TEST
DO 4 5 GND
DO
57