MPEG BOARD UD705 ZR36748 (VIDEO DAC ENCODER)
Pin No.
Pin Name
1
VDDP
2
DUPRD
3
BOOTSEL2
4
GPCI014
5
GPCI013
6
GPCI012
7
SSCRRO/CPC1011
8
SSCRRO/CPC1010
9 to 14
ATDD5 to 10
15
GNDP
16
ATDD4
17
VDDP
18
ATDD11
19
ATDD3
20
ATDD12
21
ATDD2
22
ATDD13
23
ATDD1
24
ATDD14
25
ATDD0
26
ATDD15
27
ATIOW
28
VDDC
29
ATIOR
30
GNDP
31
ATIORD
32
ATIOFFRO
33
GNDP
34
ATDA2
35
VDDP
36
ATDA1
37
ATDA0
38
ATCS1
39
ATCS0
40
BOOTSEL1
41
GPCI01
42
SSCSRO
43
GPC103
44
GCP104
45
GCP105
46
GCP106
47
GCP107
48
VDDP
49
SSCRXD/GPC108
50
GNDP
51
SSCRXD/GPC109
52
VDDP
53 to 55
RAMADD0 to 3
I/O
—
Power supply terminal (+3.3V)
—
Not used
—
Not used
I
LSI RST signal input from the AV decoder
—
Not used
—
Not used
I
Chip enable signal input from the system controller
I
Clock signal input from the system controller
I
DVD (RF) signal input from the AV decoder
—
Ground terminal
I
DVD (RF) signal input from the AV decoder
—
Power supply terminal (+3.3V)
I
DVD (RF) signal input from the AV decoder
I
DRFO signal input from the AV decoder
I
DACK signal input from the AV decoder
I
DFFR signal input from the AV decoder
I
DBGN signal input from the AV decoder
I
DCLK signal input from the AV decoder
—
Not used
I
DMUTE signal input
O
DVD tray open signal output
O
DVD tray close signal output
—
Power supply terminal (+1.8V)
O
LMTSW signal output from the AV decoder
—
Ground terminal
I
RDY signal input
—
Not used
—
Ground terminal
O
RF servo gain up signal output
—
Power supply terminal (+3.3V)
I
C2F signal input from the AV decoder
I
LRCK signal input from the AV decoder
I
BCK signal input from the AV decoder
I
CD DATA signal input from the AV decoder
—
Not used
I
INTDET signal input from the AV decoder
I
Not used in this set. Fixed at ("L").
I
WRO signal input from the AV decoder
—
Not used
O
Serial data output to the audio DAC
O
Serial data clock output to the audio DAC
I
SPDFG signal input
—
Power supply terminal (+3.3V)
I
Data signal input from the system controller
—
Ground terminal
I
Data signal input from the system controller
—
Power supply terminal (+3.3V)
O
Address bus to the D-RAM
Description
HCD-DV2D
47