Right And Left Channel Feedbeside; Vertical Amplifier; Delay-Line Compensation - Tektronix 7140 Instruction Manual

Theory of Operation-7104
complementing LO voltage is +3 .5 V . To select a channel,
to appear larger than the midband gain . To correct this, a
the HI level must be applied to the On input of U668 (pin
portion of the input signal is picked off through R502 and
2 for LEFT, and pin 12 for RIGHT VERTICAL MODE
R504 and applied to U508 . This differential signal is
switch positions) and the LO level must appear at the
converted to a single-ended signal and distributed into
OFF input (pin 1 for LEFT, and pin 11 for RIGHT
four RC (resistive-capacitative) networks, each having a
VERTICAL MODE switch positions) . To inhibit a channel
different time constant . Variable components R512,
the control voltages should be reversed .
R515, R520, R525, R530, and C538 are adjusted to
provide an accumulated waveform . This waveform is
When the VERTICAL MODE switch is set to LEFT the
converted to a paraphase signal by 0538, 0542 and
Display Right line, entering on P680 pin 6, is set LO
0548, and is then injected into U668 through pins 6 and
(-0.6 V), the Add line (P680 pin 5) is LO (0 V) and, normally,
4, where it is subtracted from the signal entering U668 at
X-Y Inhibit is LO (-0.6 V) . Transistors 0652, 0658 and
Pins 7 and 9 . Proper adjustment results in flat-frequency
0558 are turned on ; 0656 and 0556 are off. The result
response and optimum-transient response at the output
is pins 1 and 12 of U668 are pulled down to +3 .5 V but
Pins 3 and 13 .
pins 2 and 11
are only pulled down to +4 .0 V.
Consequently, the LEFT VERT channel is turned on while
the RIGHT VERT channel is turned off . Signals appearing
at J602 and J603 are amplified and fed to the outputs at
J592 and J694 . Similarly, if Display Right is HI (+1 V), the
VERTICAL AMPLIFIER
RIGHT VERT channel is turned on and LEFT VERT
channel off. RIGHT VERT channel signals are amplified
and fed to the outputs . LEFT VERT channel signals are
A schematic diagram of the Vertical Amplifier is given on
terminated within U668 .
diagram 9, in section 8_ of this manual (Diagrams and
Circuit Board Illustrations) . The schematic is divided by
When the VERTICAL MODE switch is set to either ALT or
gray shaded lines separating the circuitry into major
CHOP, the Display Right signal line switches between
stages .
These stages
aid in locating
components
the LO and HI levels at a rate determined by either the
mentioned here . Sub-headings in the following
Chop Counter or Vertical Binary stages (see Logic
discussion use the stage names to further identify
description diagram 4) .' This action displays the signal
Portions of the circuitry on diagram 9.
from the left vertical unit when the Display Right signal
line is LO and displays the signal from the right vertical
The Vertical Amplifier circuit provides final amplification
unit when the signal line is HI .
for the vertical signal received from delay-line DL694
before it is applied to the crt vertical deflector . In addition,
When ADD vertical mode operation is selected, the Add
low-frequency signals to provide the VERT TRACE
signal line is HI, and the Display Right signal is LO . This
SEPARATION (B) function and crt scale factor readout are
allows both the right and left vertical signals to pass to
accepted at the Aux Y-Axis and Y Readout inputs,
the output of U668 . The signals from both vertical units
respectively . The vertical portion of the BEAMFINDER
are
algebraically added and
the resultant signal
function is also handled in the Vertical Amplifier.
determines the vertical deflection . The X-Y Inhibit
command has absolute control over the output of the DELAY-LINE COMPENSATION
Channel Switch stage. Ouiescently, this signal is LO ;
however when the Readout System is ready to display
Delay-line DL694 delays the vertical signal approximately
information on the crt, this level goes HI, to block the
51 nanoseconds to allow the horizontal circuits time to
signals from both vertical units .
initiate a sweep before the vertical signal reaches the crt
vertical deflector . This allows the instrument to display
the triggering event when using internal triggering . The
When X-Y Inhibit is HI (+1 V) 0652 is turned off. Current
delay-line is composed of a matched pair of 50 ohm
in R653 now flows through CR552 and CR654 lowering
coaxial cables . The signal from the delay lines is coupled
the base voltage of 0556 by one diode drop, and that of
on to the 50 ~2 microstrip via J702 and J704 . Transient
0658 by two diode drops. This ensures that 0558 and
response front-corner adjustment is provided by RLC
0656 are turned on regardless of the state of Display
network R705, C705 and parasitic inductance of C705 .
Right or Add.
Hybrid circuit U762 and its associated circuitry provides
RIGHT AND LEFT CHANNEL FEEDBESIDE
frequency compensation to offset delay line losses due to
"skin-effect" in the cable. This compensation is achieved
The operation of the Left and Right Channel Feedbeside
by
attenuating the
signal at
low-frequencies
stages are identical. Therefore, only a discussion of the approximately 4.8 dB . At high frequencies (above 1 .5
Right Channel Feedbeside is given .
gigahertz) the signal passes with little attenuation . Hybrid
circuit U762 also terminates the delay line in its
The function of the Feedbeside stage is to compensate
characteristic
impedance (50 ohms) for frequencies
for
low-frequency imperfections
in
the
frequency
greater than about 50 MHz. At dc, U762 presents an
response of the Channel Switch stage, U668 . Self
impedance of 41 S2 to each cable; reverse termination of
heating of the transistor base-emitter junction, in some
U668 . Vertical Channel Switch, prevents standing waves
transistors within U668, causes the low-frequency gain
below 50 MHz.
3- 54
REV NOV 1985