Panasonic CQ-VD7005U Service Manual page 9

Pin Port
No.
54 IP SCK IP Serial clock output
55 IP STR IP STR control
56 IP RESET IP RESET output
57 NC NC(OPEN)
58 NC NC(OPEN)
59 AVREF Reference voltage input 0 of A/D
converter
60 AVSS A/D converter grand potential
61 XG Touch panel side X with respect
to - pole
62 YG Touch panel side Y with respect
to - pole
63 XR Touch panel side X with respect
to + pole
64 YR Touch panel side Y with respect
to - pole
65 LIGHT SENS DIMMER input
66 A/D KEY A/D key input for TILT and
OPEN/CLOSE
67 A/D KEY GND connection
68 A/D KEY GND connection
69 NC Not Connected
70 TFT CLK Serial communications clock for
the main CPU
71 TFT SO/TFT Serial communications data input
COM for the main CPU
72 TFT SI/TFT Serial communications data
DATA output for the main CPU
73 Touch SW Switch output for touch panel SW
detection
74 NC NC(OPEN)
75 NC NC(OPEN)
76 NC NC(OPEN)
77 NC NC(OPEN)
78 NC NC(OPEN)
79 NC NC(OPEN)
80 BUS KILL For connected confirmation of
self adjustment treatment device
Description I/O Vol
(V)
O 0
O 0
O 0
O 0
O 0
- 4.9
- 0
I 0
I 1.2
I 0
I 1.2
I 3.9
I 4.9
I 0
I 4.9
O -
I 4.9
I 0.6
O 0.4
O 4.1
O 0
O 0
O 0
O 0
O 0
O 0
I 0
9.3. DVD Servo Block
IC501 C1AB00002402
Pin No. Port
1 VDDIO I/O pad power (3.3V)
2 MD10 SDRAM data bus
3 MD11 SDRAM data bus
4 VDD Core power (1.8V)
5 MD12 SDRAM data bus
6 VSSIO I/O pad ground
7 MD13 SDRAM data bus
8 MD14 SDRAM data bus
9 MD15 SDRAM data bus
10 VDDIO I/O pad power (3.3V)
11 /DQM1 SDRAM data byte enable
12 MA9 SDRAM address bus
13 MA8 SDRAM address bus
14 VSSIO I/O pad ground
15 MA7 SDRAM address bus
16 MA6 SDRAM address bus
17 VSS Core ground
18 MA5 SDRAM address bus
19 VDDIO I/O pad power (3.3V)
20 MA4 SDRAM address bus
21 MA3 SDRAM address bus
22 MCLK SDRAM clock
23 VSSIO I/O pad ground
24 CKE SDRAM clock enable
25 MA2 SDRAM address bus
26 MA1 SDRAM address bus
27 VDDIO I/O pad power (3.3V)
28 MA0 SDRAM address bus
29 MA10 SDRAM address bus
30 MA11 Not used
31 VSSIO I/O pad ground
32 MA12 SDRAM address bus
33 MA13 SDRAM address bus
34 VDD Core power (1.8V)
35 /CS0 SDRAM primary bank chip
select
36 VDDIO I/O pad power (3.3V)
37 /RAS SDRAM command bit
38 /CAS SDRAM command bit
39 /WE SDRAM command bit
40 VSSIO I/O pad ground
41 /DQM0 SDRAM data byte enable
42 /DQM2 SDRAM data byte enable
43 MD16 SDRAM data bus
44 VDDIO I/O pad power (3.3V)
45 MD17 SDRAM data bus
46 MD18 SDRAM data bus
47 VSS Core ground
48 MD19 SDRAM data bus
49 VSSIO I/O pad ground
50 MD20 SDRAM data bus
51 MD21 SDRAM data bus
52 MD22 SDRAM data bus
53 VDDIO I/O pad power (3.3V)
54 MD23 SDRAM data bus
55 MD24 SDRAM data bus
56 MD25 SDRAM data bus
57 VSSIO I/O pad ground
58 MD26 SDRAM data bus
59 MD27 SDRAM data bus
60 MD28 SDRAM data bus
61 MD29 SDRAM data bus
62 VDDIO I/O pad power (3.3V)
63 MD30 SDRAM data bus
64 MD31 SDRAM data bus
65 /DQM3 SDRAM data byte enable
66 /CS1 Not used
67 VSSIO I/O pad ground
68 SPDIF S/PDIF digital audio output
69 VSS Core ground
9
Descriptions I/O Vol
(V)
- 3.3
I/O
I/O 0.6
- 1.8
I/O
-
I/O 0.7
I/O 0.5
I/O
- 3.3
O
O
O
-
O 2.3
O 1.9
-
O 1.1
- 3.3
O 2.0
O 2.3
O 1.7
-
O 3.3
O 2.3
O 1.0
- 3.3
O 1.0
O
-
-
O 2.1
O 2.1
- 1.8
O 2.7
- 3.3
O 3.1
O 2.9
O 3.2
-
O
O
I/O 0.5
- 3.3
I/O 0.5
I/O 0.5
-
I/O 0.7
-
I/O
I/O 1.5
I/O 1.0
- 3.3
I/O
I/O 0.5
I/O 0.5
-
I/O 0.5
I/O 0.8
I/O
I/O 1.0
- 3.3
I/O 0.7
I/O 0.5
O
O
-
O 1.3
-
CQ-VD7005U
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
-
0
0