Se-521 - Sony DSR-1500 Service Manual

DSR-1500 (UC) : S/N 100001 and Higher
DSR-1500 (J) : S/N 300001 and Higher
DSR-1500P (CE) : S/N 400001 and Higher
3
1
TO (1/3)
11
2
25
3
TO (1/3)
TO (1/3)
4
SSS-10 (2/3)
IC401
S400 (1/2) 16
15
I/F CONTROL
IC500
86 CTL
IO55
BUFF
H_NTSC/L_PAL 168 24
IO114 IO17
108 R_FLTT
LTC_DIN 83
IO70 IO53
LTC–DOUT 109 21
IO14
IO71
82 P_FLTT
IC510 BOFF IO52
WA1T 115
20
IO77 IO13
IC510
89 TBC_RE
BUFF IO58
112 88 FRRE
IRQ5
IO74 IO57
111 BANK
IRQ6 87
IO73 IO56
110 17 SV_1/2_VD
IRQ7
IO72 IO11
41 L/C_M_DRIVE
IO27
LOAD/NG_FG
23
IO16
IC517 INV 44 SV_R_SCK
FPGA_DONE 104 IO30
DONE
46 SV_R_SO
IO32
45 SV_R_SI
IO31
47 SV_SCK1
IO33
125-127,129
49 SV_SO
IO35
132-136
A0-A12 IO95
48 SV_SI
138-142
ı IO34
13 IO83
75-73
PC0-PC7
IO50
71-67
ı
IO43
8
152-146
D0-D7 IO103
142
ı
IO96
8
119
CS8
IO78
120
CS9
IO79
94
WRL 114
IO76 IO60
113 96
RD
IO62
IO75
95
IC504 IO61
97
FPGA_CS AND
155 IO63
CCLK 99
SCK
IO65
153
SO 98
IO104 IO64
107
FPGA_INIT
INIT
106 18 SV_REF_150
L_RESET
IO12
PROGRAM
80
SY_SYS_CK
GCK0
90
NSG_OE
IO59
63
CS1
IO42
62
CS2
IO41 206-199
IO139
61
CS3 195-191
IO40 ı
59 IO0
A0
IO38
58
WR
IO37
57
RD
IO36
10-3
IO7
ı
IO0
X400 40MHz
189 PLD_CS
77
IO126
GCK1
187 WRH
IO124
IC402
181 RD
IO123
OSC
14 SV_INT0
IO8
15 SV_INT1
IO9
16 SV_INT2
IO10
84 FRAME PULSE
IO54
PORT F0
179
S400
188 SV_WAIT
PORT F1
178 IO121 IO125
(2/2)
PORT F2 ı
176 22 CAPSTAN_FG_A_AC
IO15
PORT F3 IO118
175
27 CAPSTAN_FG_A_DC
PORT F5 IO116
173
IO18
IO115
PORT F6 172 29 CAPSTAN_FG_B_DC
IO19
6 30 S_REEL_FG (A)
IO20
31 S_REEL_FG (B)
IO21
33 T_REEL_FG (A)
IO22
34 T_REEL_FG (B)
IO23
IC400
35 CAPSTAN_DRIVE_PWM
IO24
VCC/NT1 36 S_REEL_DRIVE_PWM
2.5V
+3V
ı IO25
REG
VCC/NT12 37 T-REEL_DRIVE_PWM
IO26
FPEA_DONE, L_RESET
SSS-10 (2/3)
15
IC403, IC404
CH1P SELECT
14
CS0
0
PC0 CS1
A
1
CS2
PC1
B 2
PC2 CS3
C
3
PC3 CS4
D
4
CS5
5
CS6
6
CS7
7
CS8
8
CS9
9
CS10
10
IC405
CHIP SELECT
10
CS0
0
PC4 CS1
A
1
CS2
PC5
B
2
PC6 CS3
C
3
PC7 CS4
D
4
CS5
5
CS6
6
SP_R_SCK
SP_R_SO
SP_R_SI
SP_P_SCK
SP_P_SO
SP_P_SI
IC406
A, SW
IC509
BUFF
A1-A12
13
D8-D15
8
IC101
+6V 5V REG +5V-2
13-18 13-18
CTL
51-40
MB 51-40
R-FLTT
51-36 MB 51-36
P-FLTT
51-34
MB 51-34
TBC-RE
51-38 MB 51-38
FRRE
51-39 MB 51-39
BANK
51-42
MB 51-42
SV_1/2_VD
52-9 MB 52-9
L/C_M_DRIVE
52-42 MB 52-42
LOADING_FG
52-43
MB 52-43
SV_R_SCK
52-38 MB 52-38
SV_R_SO
52-37 MB 52-37
SV_R_SI
52-36
MB 52-36
SV_SK1
52-81 MB 52-81
SV_SO1
52-77
MB 52-77
SV_SI1
52-79
MB 52-79
CS0 D1R_F_CS
52-108
MB 52-108
CS1 D1R_T_CS
52-107 MB 52-107
CS2 V2R_CS
52-109 MB 52-109
CS3 F1R_CS
52-110 MB 52-110
CS4 SIFR_CS
52-105 MB 52-105
CS5 A1F_F_CS
52-102 MB 52-102
CS6 A1F_T_CS
52-101 MB 52-101
CS7 A1R_F_CS
52-100 MB 52-100
CS8 A1R_T_CS
52-99
MB 52-99
CS9 AIFI_CS
52-85 MB 52-85
CS10 ACTL_CS
52-98 MB 52-98
CS0
D1P_F_CS
52-91 MB 52-91
CS1 D1P_T_CS
52-92 MB 52-92
CS2
V2P_CS
52-90 MB 52-90
CS3
F1P_CS
52-89 MB 52-89
CS4 SIFE_CS
52-88 MB 52-88
CS5
SIFP_CS
52-94 MB 52-94
CS6 AIFP_CS
52-97 MB 52-97
SP_R_SCK
52-76 MB 52-76
SP_R_SO
52-72 MB 52-72
SP_R_SI
52-74 MB 52-74
SP_P_SCK
52-75 MB 52-75
SP_P_SO
52-71 MB 52-71
SP_P_SI
52-73 MB 52-73
D1R_J_SWP
51-37 MB 51-37
REC_SW_PULSE
52-49 MB 52-49
TO (3/3)
33
5
TO (3/3)
10
6
TO (3/3)
2
FPGA_DONE, L_RESET
4
Super Syscon/Servo
SSS-10 (2/3)
LOT NO. 072-
DSR-1500/1500P