EN 28
8.
TPM3.1E LA
8.7
TPA3123D2PWPR (IC U6301)
Block Diagram
AVCC
LIN
AGND
SD
MUTE
BYPASS
GAIN1
GAIN0
RIN
Pin Configuration
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
2009-Jun-26
IC Data Sheets
AVDD
REGULATOR
AVDD
CONTROL
THERMAL
MUTE
CONTROL
OSC/RAMP
BYPASS
AV
CONTROL
AVDD
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
Figure 8-7 Internal block diagram and pin configuration
+
VCLAMP
-
AVDD
SC
DETECT
AVDD/2
BIAS
SC
DETECT
-
VCLAMP
+
AVDD
AVDD/2
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
18400_307_090301.eps
BSL
PVCCL
HS
LOUT
LS
PGNDL
VCLAMP
BSR
PVCCR
HS
ROUT
LS
PGNDR
090619