Philips 32PFL5404 12 Service Manual page 19

7.2.2 32" & 42" SSB Cell Layout
DDR
HDMI
VGA
7.3 MT8222TMMU
7.3.1 Function Description
Analog front end
• set of high resolution ADC with corresponding PGAs
adopting to 0.5 V to 2 V input dedicated for TV/AV/SV input
signals.
• 3 high speed ADCs dedicated for VGA/HDTV input signals
up to 160 MHz.
• All 8-bit programmable gain pre-amplifiers.
• Embedded Schmitt trigger and de-glitch circuits on H
V /SOG/SOY inputs.
sync
Video Input
Embedded input multiplexers without external switch including.
FFC
Scaler
Scart
Component
Figure 7-1 32" & 42" SSB layout
/
sync
Circuit Descriptions
• 8 for TV/AV/S-video input pins available for any possible
combination.
• 3 sets for VGA/Component/Scart/D-connector with
differential input pairs.
• 3 sets of HDMI/DVI input port with internal multiplexers.
• Input sources can be flexibly routed to Main/PIP internally.
Sync Processor
• Two enhance sync processors for all timing detection
supporting Macrovision detection.
• Enhanced measuring mechanism for VGA auto
adjustment.
Decoder
TVD
• Single high-quality 4th generation TV decoder.
TPM3.1E LA 7.
CLASS D
TUNER
HDMI
18400_206_090301.eps
EN 19
USB
AV Input
090617
2009-Jun-26