Sensor Block Diagram - Panasonic AG-EZ50UP Service Manual

7.2.

SENSOR BLOCK DIAGRAM

CCD FLEX.CARD
SENSOR
PP201 PS201
3.4 3.4
PP201 PS201
1.2 1.2
PP201 PS201
28 28
PP201 PS201
29 29
PP201 PS201
30 30
PP201 PS201
31 31
SENSOR
PP201 PS201 V SUB(G)
27 27
SENSOR
PP201 PS201
5 5
G CCD
PP201 PS201
6 6
PP201 PS201
33 33
LENS UNIT R CCD
PP201 PS201
34 34
PP201 PS201
LIGHT
13 13
PP201 PS201
14 14
PP201 PS201
12 12
3CCD METHOD
B CCD
SENSOR
PP201 PS201
23 23
PP201 PS201
22 22
PP201 PS201
21 21
PP201 PS201
20 20
PP201 PS201 V SUB(R)
32 32
PP201 PS201 V SUB(B)
15 15
SENSOR
PP201 PS201
V.OUT(G)
10 10
PP201 PS201
V.OUT(R)
8 8
PP201 PS201
V.OUT(B)
17 17
IC101
IC107 (V.DRIVER(G))
CH1 G CH1
8 31
CH2 G CH2
13 32
VH
16 CAM15V
VHH
15V 20
-8V
V1(G)
INPUT VL
5 2 CAM -8V
I/F
V2(G)
V1 G V1
3 7 27
V3(G)
V2 G V2
17 9 28
V4(G)
V3 G V3
18 14 29
V4 G V4
12 30
SUB SUB
1 10 33
IC109(H.DRIVER)
H2(G) H2
10 11 36
H1(G) H1
4 3 37
H1(R) R
2 1 38
H2(R)
12 13
H1(B)
6 5
H2(B)
8 9
R
IC108 (V.DRIVER(R.B))
V1(R.B) V1 R.B
5 7
V2(R.B) V2 R.B
3 9
V3(R.B) V3 R.B
17 14
V4(R.B) V4 R.B
INPUT
18 12
I/F
SUB
1 10
CH1 R.B
8
CH2 R.B
13
VH
16
VHH CPOB 11
20
HD2 15
HD 16
VD 17
VL VD2 18
2
(CCD DRIVE,PULSE GEN)
DS1
46
DS2
47
X101
FCK2I2
1/2 64
(22.5MHz)
FCK0
4
2FCK0
TO
HIGHSPEED 1
PROCESS
PULSE
DECODER
ELECTRIC
SHUTTER
SUB PULSE
CONTROL
FROM
10 CS
CONTROL
SERIAL
8
DATA IN
9
FROM
PROCESS
CH PULSE
DECODER
V PULSE
DECODER
PROCESS
PULSE
DECODER
V TIMING
HCLR GEN H TIMING
24
:MAIN SIGNAL PATH IN REC MODE
IC104 (CDS/AGC/AD)
32
TIMMING
33
GEN
34
38 SERIAL
39 REG
OSC
V OUT(G) 8 CDS AGC
V OUT(R) 3
V OUT(B) 18
CDS AGC
CDS AGC
57
A/D G DATA
66
67
A/D 69
R DATA TO
72
PROCESS
78
45
A/D 51
B DATA
54
56