Measurement Logic Section - Keithley 776 Instruction Manual

Theory of Operation
The reference oscillator also contains a phase noise
generator. During certain measurement functions, this
generator injects phase noise to the reference oscillator.
The noise generator is comprised of CR3, bias resistor
R9, and operational amplifier - U7. The noise generator
is switched in and out by an analog switch - U8 and is
controlled by 42 and its associated components.
6-3-5. Measurement Logic Section
The measurement logic section is a block which con-
trolsvarious switching, routes the internal signals to the
correct ports. It also controls the sequence of the gate
and resets and synchronizes the main registers Nl and
N2 for the CPU. Figures 5-4 to 5-9 show the routes for
the input signal and the reference signal in every meas-
urement function. The following is a brief explanation
of the various segments in the measurement logic sec-
tion.
Control: The control circuit consists of U15, U14,
and U13. Information from the CPU is sent in a serial
form to the control ICs which in term convert the serial
information to a parallel format. The parallel outputs of
these ICs are being used to control the signal selectors,
and the signal routing to the various sections within the
measuring logic section. Qll through 413 convert the
TTL logic levels from the CPU to an appropriate voltage
levels for U15 (0 V to -5.2 V).
Signal Selector: The signal selector circuit com-
prises U19, U20, U21, U25, and U28. The function of
the signal selector is to route one of Channel A input.
Channel B input, Channel C input. or the reference
clock to the appropriate processing sections.
Time Interval Section:
The time interval section
circuit consists of ti dual D flip-plop U 17a/b. and gates
U18a, b and c, and Ul9b. U17a receives the start signal.
and U17b receives a stop signal. Following a reset
signal at the reset input of U17a/b, U18c simultaneously
produces a single positive pulse (TI), and its comple-
ment with a duration which is equal to the time interval
between the start, and the stop signals, regardless if the
start and stop signals are repetitive. While performing
time averaged measurements, these pulses will repeat as
long as the gate stays open.
Synchronizer #l:
The synchronizer #l consists of a
D flip flop U22b. gate U26b/d, and their associated
components. During reciprocal frequency measure-
ment, a gate signal is applied from the CPU to the D
input of U22d. and the measured signal is coupled to the
CLK input on the same IC. After a reset cycle, and
assuming that a signal is present at the appropriate input
terminal, the output of U22b generates a pulse with an
approximate width of the original gate signal from the
CPU. but with a new adjusted width which is equal to
an integer number of periods of the signal being meas-
ured. This pulse is used as the #I synchronized (SGT 1)
gating signal throughout the instrument. In conven-
tional frequency measurements, (refer to the above de-
scription), the gate time is synchronized to the reference
clock 1 (1.25 MHz). SGT 1 opens the gate U26d for the
appropriate signal to be later divided, and counted by
Nl dividing chain.
Synchronizer #2:
The
synchronizer
#2 consists of a
D flip flop U29b, gate U28d, and their associated com-
ponents. During reciprocal frequency measurement,
SGT 1 signal is applied to the D input of U29b. At the
same time, the reference clock 2 (500 MHz) is applied
to the CLK input on the same IC. the output of U29b
generates a pulse SGT 2 with an approximate width of
SGT 1, but with a new adjusted width which is equal to
an integer number of periods of the reference clock 2.
In conventional frequency measurements, the gate time
is synchronized to the input signal. SGT 2 opens the gate
U28d for the appropriate signal to be later divided and
counted by N2 dividing chain.
Signal Identifier:
The signal identifier comprises
U22a. U31a, and their associated components. A signal
when present at the appropriate input terminal, is ap-
plied to the CLK input of U22a, converted to a TTL
level signal with U3 la, and then fed to a CPU port 1.1.
This port is used to flag the presence of a signal at the
input terminals. This signal is also used as the arming
signal of the counter.
Gate Identifier:
The gate identifier informs the CPU on
the state of the synchronized gate time # 1. The gate identifier
circuit also serves as a time stretcher of gate signals having
very small periods. The gate identifier consists of U26a,
U26c. U31d, R158, and C86.
Nl Counter Chain: The Nl counter chain comprises
U30b, U31a. U27a, U23a, U46a, U44, and their associated
components. U3Ob, U27a, U23a, and U46a are configured
as 7 bit binary up counter
with
its output connected to U44.
U44 is a 32 bit counter with its outputs connected to the data
bus. U31c converts the ECL logic level from U30b to Tn.
N2 Counter Chain:
The N2 counter chain comprises
U29a, U3Oa, U3lb. U27b, U23b, U46b. U45, and their
associated components. U29a, U3Oa, U27b, U23b, and
U46b are contigured as 8 bit binary up counter with its
output connected to U45. U45 is a 32 bit counter with its
outputs connected to the data bus. Ql5 and U31b convert
the ECL logic level from U29a, and U30a respectively to
T-l-L.
6-13