Noise Reduction; Noise Measurement; Operation Modes; Digital 656 Output - Daewoo DTF-2950-100D Service Manual

pixels by subsampling. To prevent the introduction of alias distortion low pass filters are used for
luminance and chrominance processing. The horizontal prescaler consists of two main
subsampling stages. The first stage is a scaler for rational decimation factors in a range of 1 to 2.
The second stage decimates in integer steps (1,2,3,4...32).

5.3.1.8.2 Noise Reduction

The structure of the temporal motion adaptive noise reduction is the same for luminance as for
chrominance signal.
The output of the motion detector is weighted. The look-up table input value range is separated
into 8 segments. It is possible to freely program different behaviour of the noise reduction by
using predefined curve characteristic for each segment.

5.3.1.8.3 Noise Measurement

The noise measurement algorithm is used to sort program during ATSS. This is done by the TV-
microcontroller which reads the noise level in VSP. The value is determined by averaging over
several fields.

5.3.1.8.4 Operation Modes

The interlaced input signal (e.g. 50 Hz PAL or 60 Hz NTSC) is composed of a field A (odd lines)
and a field B (even lines). The 100Hz operation mode used is simply AABB, where each stored
field in the memory is displayed double times on the TV screen.
A still field can be displayed using FREEZE command, the operation mode becomes ABAB.

5.3.1.8.5 Digital 656 Output

The output data format corresponds to CCIR 656 with double-scan format (8-bit bus at a data
rate of 54 MHz). There all frequencies and data-rates are doubled compared to standard
CCIR656 specification. Timing reference codes (SAV, EAV) are inserted according to the
specification. The output is set to 720 pixels per line and the display clock is set to 54 MHz.

5.4.2 BACK END

5.4.2.1 Digital Input Interface

The digital input interface is set to receive 8 bit 4:2:2 Y Cr Cb multiplexed with separate H/V-
syncs and clock (ITU-R-656 format). The data inputs Y0...Y7 and C0...C7 are clocked with the
external clock LLC2. The clock frequency is 54 MHz for 8 bit data input. The horizontal sync
pulse at the HS pin should be an active video signal, which is not vertically blanked. A clock
generator converts the different external line locked clock rates to a common internal sample rate
of approximately 40.5 MHz, in order to provide a fix bandwidth for all digital filters. Therefore the
input data is sample rate converted to the common processing frequency by the horizontal scaler.

5.4.2.2 Horizontal Scaler

The horizontal scaler supports linear or nonlinear horizontal scaling of the digital input video
signal in the range of 0.25 to 4. Nonlinear scaling, also called "panorama vision", provides a
geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9
screen by stretching the picture geometry at the borders. Also, the inverse effect can be
produced by the scaler. See also microcontroller section to find details on format switching logic.
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