H13 Block Diagram (Internal) - LG 55UB8500 Service Manual

H13 Block Diagram (Internal)

Analog Chip Total Pin : 183w/o Power
H13A
GBB AFE
DIF
1ch@30MHz
w/ PLL
Tuner
SIF
BTSC AFE
10b@18.432MHz
w/ PLL
1ch L/R
Audio L/R(4-
Audio-ADC
ch)
24b@48KHz
SCART out
Audio DAC
(48KHz )
Line Out
Audio DAC (48KHz)
CVBS(3ch)
CVBS DAC CVBS DAC
CVBS-Out CVBS AFE(2-ch)
12b@54MHz
3ch Video
AFE
Component(2ch)
10b@148.5MHz
w/ LLPLL
I2Cx1
I2Cx1
HDMI
AtoDPin : 79
SDRAM
(MCP)
TS (P) TS (P)
Global Baseband Gl b l B b d
V/Q, DVB-T/C ISDB-T
I2S(External)
I2S
I2S
I2S
I2S(HPD)
Digital AMP
SPDIF
5x1ch (1ch)
10x3ch
Capture
LVDS
Block
Tx Tx
(3CH)
Audio PLL
w/ DCO
GPIOIx16
DVB-CI/CI+
H13D
TS(P) TS(P) TS(S)
TS(S)
Video Decoder
System
M lti STD Multi-STD
Demux
HD Decoder
(Boda950)
AAD
(THAT)
Audio DSP
Audio
Multi-STD
Video Encoder
Audio Decoder
LX4 HiFi EP
1080p@30fps
Sound DSP
Clear Voice II
ARMCA9 Core
Perceptual
Dual 1.2GHz
Volume Control Volume Control
Slim SPK
32KBI$
Digital
DivX
1MB L2 $
Audio
Bluetooth
Output
CVBS
Encoder
CVD DE
Y/C
MCU
CVBS
LVDS
Rx Rx
HDMI
(1-Link)
HDMI-Rx 1.4
( (1-port PHY) p ) DDR3 Controller DDR3 Controller
3D, ARC, 4kx2k
DDR3 PHY
16
Digital Chip Total Pin : 491w/o Power
GPU Rogue Han g
2D GFX
JPG/PNG Decoder
JPG Encoder
p@ p
TrustZone
CPU
Secure Engine
CPU
48KB ROM
64KB SRAM
OTP
32KBD$
UART
Timer
BE
MCU
DDR3 Controller DDR3 Controller
DDR3 PHY
8
USB2.0x3
UARTx3
GPIOx136
EMAC
SCI
SPIx2
I2Cx10 I2C 10
USB3.0 x1
eMMC
DMAC(8ch)
Timer
WDT WDT
SRAM 16KB
DCO
CPLL
x2
SPLL DPLL
DDR DDR
PLL PLL
LGE Internal Use Only