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TERMINATION
AT E5.1
4
E5_SDRAM_DQ[31..0]
2
RP1
51/RP
E5_SDRAM_DQ0
SDRAM_DQ0
8
1
E5_SDRAM_DQ1
7
2
SDRAM_DQ1
E5_SDRAM_DQ2
SDRAM_DQ2
6
3
E5_SDRAM_DQ3
SDRAM_DQ3
5
4
RP3
51/RP
E5_SDRAM_DQ4
SDRAM_DQ4
1
8
E5_SDRAM_DQ5
SDRAM_DQ5
2
7
E5_SDRAM_DQ6
3
6
SDRAM_DQ6
E5_SDRAM_DQ7
SDRAM_DQ7
4
5
RP5
51/RP
E5_SDRAM_DQ8
SDRAM_DQ8
8
1
E5_SDRAM_DQ9
SDRAM_DQ9
7
2
E5_SDRAM_DQ10
6
3
SDRAM_DQ10
E5_SDRAM_DQ11
SDRAM_DQ11
5
4
RP7
51/RP
E5_SDRAM_DQ12
8
1
SDRAM_DQ12
E5_SDRAM_DQ13
SDRAM_DQ13
7
2
E5_SDRAM_DQ14
SDRAM_DQ14
6
3
E5_SDRAM_DQ15
5
4
SDRAM_DQ15
RP9
51/RP
E5_SDRAM_DQ16
8
1
SDRAM_DQ16
E5_SDRAM_DQ17
SDRAM_DQ17
7
2
E5_SDRAM_DQ18
SDRAM_DQ18
6
3
E5_SDRAM_DQ19
5
4
SDRAM_DQ19
RP11 51/RP
E5_SDRAM_DQ20
SDRAM_DQ20
1
8
E5_SDRAM_DQ21
2
7
SDRAM_DQ21
E5_SDRAM_DQ22
SDRAM_DQ22
3
6
3
E5_SDRAM_DQ23
SDRAM_DQ23
4
5
RP12 51/RP
E5_SDRAM_DQ24
SDRAM_DQ24
5
4
E5_SDRAM_DQ25
6
3
SDRAM_DQ25
E5_SDRAM_DQ26
SDRAM_DQ26
7
2
E5_SDRAM_DQ27
SDRAM_DQ27
8
1
RP14 51/RP
E5_SDRAM_DQ31
SDRAM_DQ31
1
8
E5_SDRAM_DQ28
SDRAM_DQ28
2
7
E5_SDRAM_DQ30
3
6
SDRAM_DQ30
E5_SDRAM_DQ29
SDRAM_DQ29
4
5
RP16 22/RP
E5_SDRAM_DQM0 2
SDRAM_DQM0
1
8
E5_SDRAM_DQM1 2
2
7
SDRAM_DQM1
E5_SDRAM_DQM2 2
SDRAM_DQM2
3
6
E5_SDRAM_DQM3 2
SDRAM_DQM3
4
5
RP18 22/RP
E5_SDRAM_A1 2
8
1
SDRAM_A1
E5_SDRAM_A6 2
SDRAM_A6
7
2
E5_SDRAM_A3 2
SDRAM_A3
6
3
E5_SDRAM_A15 2
5
4
SDRAM_A15
RP20 22/RP
E5_SDRAM_A8 2
SDRAM_A8
1
8
E5_SDRAM_A0 2
SDRAM_A0
2
7
E5_SDRAM_A4 2
SDRAM_A4
3
6
E5_SDRAM_A2 2
SDRAM_A2
4
5
RP22 22/RP
E5_SDRAM_A7 2
SDRAM_A7
8
1
E5_SDRAM_A14 2
7
2
SDRAM_A14
2
E5_SDRAM_A9 2
SDRAM_A9
6
3
E5_SDRAM_A12 2
SDRAM_A12
5
4
RP24 22/RP
1
8
E5_SDRAM_A11 2
SDRAM_A11
2
7
E5_SDRAM_A10 2
3
6
SDRAM_A10
E5_SDRAM_A5 2
SDRAM_A5
4
5
E5_SDRAM_DQS0 2
R44
51
SDRAM_DQS0
E5_SDRAM_DQS1 2
R45
51
SDRAM_DQS1
E5_SDRAM_DQS2 2
R47
51
SDRAM_DQS2
E5_SDRAM_DQS3 2
R49
51
SDRAM_DQS3
E5_SDRAM_CLK0 2
R52
22
SDRAM_CLK0
E5_SDRAM_CLK1 2
R53
22
SDRAM_CLK1
E5_SDRAM_CLK#0 2
R55
22
SDRAM_CLK#0
E5_SDRAM_CLK#1 2
R57
22
SDRAM_CLK#1
RP26
22/RP
E5_SDRAM_RAS# 2
SDRAM_RAS#
1
8
E5_SDRAM_CLKE 2
2
7
SDRAM_CLKE
E5_SDRAM_CAS# 2
SDRAM_CAS#
3
6
E5_SDRAM_WE# 2
SDRAM_WE#
4
5
E5_SDRAM_CS0 2
R65
22
SDRAM_CS0
1
A
B
SSTL2_VDD
4
SDRAM_DQ[31..0]
C57
C58
104
104
C61
C62
104
104
SSTL2_VDD
C64
C65
104
104
C70
C71
104
104
SSTL2_VDD
C76
C77
C78
C79
C80
C81
104
104
103
103
104
104
C89
C90
C91
C92
C93
C94
104
104
103
103
104
104
DDR TERMINATION VOLTAGE REGULATOR
VREF needs to be decoupled
to both SSTL2_VDD and SSTL2_GND with balanced
decoupling capacitors.
VREF should be routed over a
reference plane and isolated, and possibly
shielded with both SSTL2_VDD and SSTL2_GND
VREF
2,4
VREF
C107
104
B
C
TERMINATION
AT DDR
The VTT side of the terminaton resistors should be placed
on a wide VTT island on the surface layer. The island is
located at each end of the bus, so it does not interfere
with the signal routing.
C59
C60
103
103
VREF
VREF
2,4
C63
103
GND_SSTL2
C66
C67
C68
C69
103
103
104
104
VTT
VTT
C72
C73
C74
C75
103
103
104
104
GND_SSTL2
SSTL2_VDD
C82
C83
C84
C85
C86
102
102
102
104
104
VTT
VTT
C95
C96
C97
C98
C99
102
102
102
104
104
GND_SSTL2
GND_SSTL2
VTT
CA3
+
C102
+
220u/16
10u/16
U2
1
8
NC
VTT
2
7
SSTL2_VDD
GND
PVIN
3
6
VSENSE
AVIN
4
5
VREF
VDDQ
LP2995
C106
+
CA4
220u/16
104
GND_SSTL2
C
26
D
4
SDRAM_DQ[31..0]
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
C87
C88
SDRAM_DQ28
102
102
SDRAM_DQ29
SDRAM_DQ30
VREF
SDRAM_DQ31
VREF
2,4
C100
C101
SDRAM_A0 4
102
102
SDRAM_A1 4
SDRAM_A2 4
SDRAM_A3 4
SDRAM_A7 4
SDRAM_A6 4
SDRAM_A5 4
SDRAM_A4 4
SDRAM_A12 4
SDRAM_A11 4
SDRAM_A9 4
SDRAM_A8 4
SDRAM_RAS# 4
SDRAM_A14 4
SDRAM_A15 4
SDRAM_A10 4
SDRAM_DQS0 4
R46
SDRAM_DQS1 4
R48
SDRAM_DQS2 4
R50
C104
+
C103
C105
SDRAM_DQS3 4
R51
104
T47u/16
104
SDRAM_DQM0 4
R54
SDRAM_DQM1 4
R56
SDRAM_DQM2 4
R58
SDRAM_DQM3 4
R59
SDRAM_CLK#0 4
R60
SDRAM_CLK#1 4
R61
SDRAM_CLK0 4
R62
SDRAM_CLK1 4
R63
SDRAM_CLKE 4
R64
SDRAM_WE# 4
R66
SDRAM_CAS# 4
R67
SDRAM_CS0 4
R68
LSI LOGIC
560 COTTONWOOD DR.
MILPITAS, CA 95035
U. S. A.
Title
TERM AT E5
Size
Document Number
C
Date:
Monday, June 07, 2004
D
E
4
VTT
RP2 51/RP
8
1
7
2
6
3
5
4
RP4
51/RP
8
1
7
2
6
3
5
4
RP6
51/RP
4
5
3
6
2
7
1
8
RP8
51/RP
4
5
3
6
2
7
1
8
RP10 51/RP
8
1
7
2
6
3
5
4
3
RP13 51/RP
8
1
7
2
6
3
5
4
RP15
51/RP
8
1
7
2
6
3
5
4
RP17
51/RP
8
1
7
2
6
3
5
4
RP19 51/RP
8
1
7
2
6
3
5
4
RP21 51/RP
1
8
2
7
3
6
4
5
RP23
51/RP
2
1
8
2
7
3
6
4
5
RP25 51/RP
8
1
7
2
6
3
5
4
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
1
Rev
D0
Sheet
3
of
12
E
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