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A
3
E5_SDRAM_A0
3
E5_SDRAM_A1
3
E5_SDRAM_A2
3
E5_SDRAM_A3
V33
3
E5_SDRAM_A4
3
E5_SDRAM_A5
3
E5_SDRAM_A6
3
E5_SDRAM_A7
R1
R2
R3
R4
3
E5_SDRAM_A8
3
E5_SDRAM_A9
3
E5_SDRAM_A10
3
E5_SDRAM_A11
10K
10K
10K
10K
3
E5_SDRAM_A12
3
E5_SDRAM_A14
TMS
3
E5_SDRAM_A15
3
E5_SDRAM_CS0
TDI
3
E5_SDRAM_CAS#
3
E5_SDRAM_RAS#
TDO
3
E5_SDRAM_CLKE
3
E5_SDRAM_WE#
TCK
3
E5_SDRAM_CLK0
3
E5_SDRAM_CLK#0
TRST_L
4
GND
3
E5_SDRAM_CLK1
3
E5_SDRAM_CLK#1
R11
10K
3,4
VREF
AO_D0
1
A17
AO_D0
R19
22
AO_1
B15
11
AO_D1
AO_D1
R21
22
AO_2
B16
11
AO_D2
AO_D2
R23
22
AO_3
B17
11
AO_D3
AO_D3
R24
22
AOSCLK
B14
11
AO_SCLK
AO_SCLK
R26
22
AOFSYNC
A14
11
AO_FSYNC
AO_FSYNC
GPIOx[31]
GPIOx[34]
R29
22
AOIEC
B13
5
AO_IEC958
AO_IEC958
1
TP1
E5_GPIOx33
A13
GPIOx[33]
AO_MCLKI
R30
22
AOMCLKO
A15
11
AO_MCLKO
AO_MCLKO
(Input Only)
C14
11
AI_D0
AI_D0
E5_GPIO6
GPIO[6]
D14
7
RDS_DATA
AI_D1
GPIO[7]
R33
22
AISCLK
A12
11
AI_SCLK
GND
AI_SCLK
R34
22
AIFSYNC
D13
11
AI_FSYNC
AI_FSYNC
TP2
E5_GPIOx32
GPIOx[32]
1
C13
AI_MCLKI
R35
22
AIMCLKO
A16
11
AI_MCLKO
AI_MCLKO
C1
27P
CLKI
E1
CLKI
3.3v only
CLKX
F1
CLKX
(Reset_Audio)
E5_GPIOx35
GPIOx[35]
H1
5,9
E5_GPIOx35
CLKO
Y1
G1
BYPASS_PLL
13.5MHZ
GND
C2
TCK
B7
TCK
27P
TDI
A7
TDI
TDO
JTAG
C6
TDO
GND
TMS
B6
TMS
TRST_L
D6
TRST_L
VI_D0
B10
VI_D0
VI_D1
C10
9
VI_D[9..0]
VI_D1
VI_D2
B11
VI_D2
VI_D3
C11
VI_D3
3
VI_D4
D11
VI_D4
VI_D5
D10
VI_D5
VI_D6
B12
VI_D6
VI_D7
C12
VI_D7
VI_D8
D12
VI_D8
VI_D9
A11
VI_D9
PEC
VI_VSYNC
A10
9
VI_VSYNC
VI_VSYNC0
VI_CLK0
A9
9
VI_CLK0
VI_CLK0
GPIOx[45]
GPIOx[29]
E5_GPIOx2
R36
10K
V33
2nd
24-bit
E5_GPIOx1
R37
10K
vin
vout
VI_D0
VI_D1
E5_GPIOx3
R38
10K
(SCART_GPIO)
VI_D2
VO_D16
E5_GPIOx4
R39
10K
(SCART_GPIO)
VI_D3
VO_D17
(SCART_GPIO)
VI_D4
VO_D18
E5_GPIOx5
R40
10K
VI_D5
VO_D19
VI_D6
VO_D20
VI_D7
VO_D21
E5_GPIOx6
R41
10K
VI_D8
VO_D22
E5_GPIOx7
R42
10K
VI_D9
VO_D23
E5_GPIOx0
GPIOx[0]
D7
(BIO_PHY_PD)
7
E5_GPIOx0
VO_D0
E5_GPIOx1
GPIOx[1]
C7
12
E5_GPIOx1
VO_D1
E5_GPIOx2
D8
GPIOx[2]
12
E5_GPIOx2
VO_D2
E5_GPIOx3
GPIOx[3]
C8
(VI_AVID)
9
E5_GPIOx3
VO_D3
E5_GPIOx4
GPIOx[4]
B8
(MIC_DET)
12
E5_GPIOx4
VO_D4
E5_GPIOx5
D9
GPIOx[5]
(MUTE)
11
E5_GPIOx5
VO_D5
E5_GPIOx6
GPIOx[6]
C9
(INT_VI)
9
E5_GPIOx6
VO_D6
E5_GPIOx7
GPIOx[7]
B9
(/RST_VI)
9
E5_GPIOx7
VO_D7
GPIOx[8]
GPIOx[9]
GPIOx[10]
GPIOx[11]
GPIOx[12]
GPIOx[13]
GPIOx[14]
GPIOx[15]
GPIOx[30]
2
A8
VO_CLK
VDENC
SEL
0
1
2
A1
10
CVBS
DAC1
CPST
Y
-
A2
10
Y
DAC2
Y CPST
-
A3
10
C
DAC3
C CPST
-
POWER
A4
10
Y/G
DAC4
G/Y
Y
-
A5
10
Pb/B
DAC5
B/Pb
C CPST
3.3V
A6
10
Pr/R
DAC6
R/Pr
C CPST
D5
DAC_Dvdd (1.8v)
V18_E5_DAC_DVDD
C6
C7
B2
DAC_Vdd0(3.3v)
104
103
B3
DAC_Vdd1(3.3v)
C5
DAC_Dvss
B4
DAC1bar
B5
DAC0bar
GND
D2
V33_E5_DAC_AVDD
IN4148
V33_E5_USB
+
C8
C9
C10
D3
C12
CA2
+
IN4148
T47u/16
104
104
103
104
C11
VO_GND
GND
10UF/1206
VO_GND
GND
1
A
B
E5_SDRAM_DQ[31..0] 3
CONTROL
ADDR
CS[9]-
SDRAM
I/F
CS[8]-
DACO
E5.1-BGA-308-A
U1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
TOP VIEW
B
C
D
E
F
G
H
J
K
L
20-bit
2nd
vin
vout
M
VI_D10
VI_D11
N
VI_D12
VO_D0
VI_D13
VO_D1
P
VI_D14
VO_D2
R
VI_D15
VO_D3
VI_D16
VO_D4
T
VI_D17
VO_D5
VI_D18
VO_D6
U
VI_D19
VO_D7
V
W
Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
USB
1394
POWER
SDRAM
PADS
CORE
SDR
GND
3.3V
1.8V
DDR
E5_VPAD
SSTL2_VDD
E5_VCORE
SSTL2_VDD
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
+
102
102
102
104
104
104
104
104
104
T47u/16
GND
E5_VDDREF
E5_AVDD
E5_VDDX
C51
C52
C53
C54
C55
C56
103
104
103
103
104
102
GND
GND
GND
B
C
E5_GPIOx25 12
(RDY_FM)
E5_GPIOx24 12
(ATN_FM)
E5_GPIOx41 12
(FP SCLK)
E5_GPIOx42 12
(FP D_FM)
IRTX1
DATA
SPI
UART1
UART2
IDC
IR
SIO
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
GND
PLL PLL
DIGITAL
3.3V
2.5V
5V
3.3V
E5_V5BIAS
104
C13
GND
GND
GND
E5_AVDD
General decoupling cap placement:
Caps with smaller capacitance values to be
E5_VDDX
closer to respective power pins compared to
those of larger values. All should be as
close as possible.
C25
C33
C34
C35
C36
C37
+
+
C24
10UF/1206
102
102
102
103
103
10UF/1206
C38
C46
C47
C48
C49
C50
+
102
102
102
103
104
10UF/1206
C
74
D
OPEN FOR DW9916
VCC
DI
9
DO
9
CL
9
CE
9
R233
R234
R235
R236
10K
10K
10K
10K
CN8
5P1.0
SPI_MOSI
DI
R237
22
1
SPI_MISO
R238
22
DO
2
SPI_SCK
R239
22
CL
3
CE
SPI_CS2
R240
22
4
E5_UART2_TX 5
5
E5_UART2_RX 5
SDA
6,7,9,11,12
GND
SCL
6,7,9,11,12
E5_VDDX
R6
*10K
D1
*1N6263
1
2
IR_FMUTE 11,12
R10
*0
SLAVE
MASTER
R20
22
Y8
ALE
E5_ALE 5,6
RST-
W15
/SYS_RST 5,6
RST-
MCONFIG
MCONFIG
G2
MCONFIG
CS-
Y11
CS0_8BIT
GND
RD-
LDS-
R27
22
Y9
OE-
/E5_OE 5,6
DMAREQ
UDS-
R28
22
V14
UWE-
/E5_UDS 5
HINT-
V6
E5_GPIO0
E5_GPIO0 12
GPIO0
A0
E5_GPIO1
V12
GPIO1
E5_GPIO1 7
A1
E5_GPIO2
W9
GPIO2
E5_GPIO2 5
A2
V8
E5_GPIO3
E5_GPIO3 11
GPIO3
PCMCIA_IOW-
E5_GPIO4
W8
GPIO4
E5_GPIO4 12
PCMCIA_IOR-
E5_GPIO5
U10
GPIO5
E5_GPIO5 12
RD
WR-
Y7
R31
22
/E5_WEL 5,6
LWE-
WAIT-
/WAIT
U8
WAIT-
/WAIT
5
DTACK-
/DTACK
R32
22
U9
DTACK-
E5_/DTACK 5
D31
W3
CS5-
D30
Y2
CS4-
D29
Y6
CS3-
D28
Y4
/E5_CS2
CS2-
D27
Y5
CS1-
/E5_CS1 5
D26
Y3
CS0-
/E5_CS0 6
D25
V4
MA[26]
D24
V5
MS[25]
D23
W4
MA[24]
D22
U5
MA[23]
D21
W5
MA[22]
E5_MA22 6
D20
U6
MA[5]
E5_MA5 5,6
D19
W7
E5_MA4 5,6
MA[4]
D18
W6
MA[3]
E5_MA3 5,6
D17
U7
MA[2]
E5_MA2 5,6
D16
V7
E5_MA1 5,6
MA[1]
D15
MA[21]
HD15
V10
D15
D14
MA[20]
W11
HD14
D14
D13
MA[19]
HD13
Y10
D13
D12
MA[18]
HD12
V9
D12
D11
MA[17]
V11
HD11
D11
D10
MA[16]
HD10
Y12
D10
D9
MA[15]
HD9
W10
D9
D8
MA[14]
W12
HD8
D8
D7
MA[13]
HD7
Y13
D7
D6
MA[12]
HD6
U11
D6
D5
MA[11]
V13
HD5
D5
D4
MA[10]
HD4
W13
D4
D3
MA[9]
HD3
Y14
D3
D2
MA[8]
U12
HD2
D2
D1
MA[7]
HD1
U13
D1
D0
MA[6]
HD0
W14
D0
5,6
SBP_FRAME
V3
AtapiAddr0
AtapiAddr0 6
SBP_ACK
T4
AtapiAddr1 6
AtapiAddr1
SBP_RD
V1
AtapiAddr2
AtapiAddr2 6
SBP_REQ
U2
AtapiAddr3
AtapiAddr3 6
SBP_CLK
U4
AtapiAddr4 6
AtapiAddr4
GPIOx[23]
SBP_D[7]
W2
ATAPI_DATA15
ATAPI_DATA15 6
GPIOx[22]
SBP_D[6]
U1
ATAPI_DATA14
ATAPI_DATA14 6
GPIOx[21]
SBP_D[5]
R4
ATAPI_DATA13 6
ATAPI_DATA13
GPIOx[20]
SBP_D[4]
R1
ATAPI_DATA12
ATAPI_DATA12 6
GPIOx[19]
SBP_D[3]
P3
ATAPI_DATA11
ATAPI_DATA11 6
GPIOx[18]
SBP_D[2]
P1
ATAPI_DATA10 6
ATAPI_DATA10
GPIOx[17]
SBP_D[1]
N2
ATAPI_DATA9
ATAPI_DATA9 6
GPIOx[16]
SBP_D[0]
M2
ATAPI_DATA8
ATAPI_DATA8 6
SD_D[7]
M3
ATAPI_DATA7
ATAPI_DATA7 6
SD_D[6]
M4
ATAPI_DATA6 6
ATAPI_DATA6
SD_D[5]
N3
ATAPI_DATA5
ATAPI_DATA5 6
SD_D[4]
N4
ATAPI_DATA4
ATAPI_DATA4 6
CD_C2PO
SD_D[3]
P2
ATAPI_DATA3 6
ATAPI_DATA3
CD_BCK
SD_D[2]
P4
ATAPI_DATA2
ATAPI_DATA2 6
CD_LRCK
SD_D[1]
R3
ATAPI_DATA1
ATAPI_DATA1 6
CD_DATA
SD_D[0]
T1
ATAPI_DATA0 6
ATAPI_DATA0
Y1
ATAPI_RESET_L
ATAPI_RESET 6
SD_SECSTART
T2
ATAPI_DMAACK_L
ATAPI_DMAACK_L 6
SD_ERROR
W1
ATAPI_DMARQ
ATAPI_DMARQ 6
SD_CLK
T3
ATAPI_IORDY
ATAPI_IORDY 6
SD_ACK
V2
ATAPI_INTRQ
ATAPI_INTRQ 6
SD_RDREQ
U3
ATAPI_DIOR_L 6
ATAPI_DIOR_L
SD_WRREQ
R2
ATAPI_DIOW_L
ATAPI_DIOW_L 6
VREF
E5_VDDREF
R43
GND
E5_VPAD
C26
C27
C28
C29
C30
C31
C32
+
104
104
104
104
104
104
10UF/1206
GND
E5_VCORE
C39
C40
C41
C42
C43
C44
C45
+
104
104
104
104
104
104
10UF/1206
GND
D
E
/DTACK
R5
10K
MCONFIG
R7
10K
V33
/E5_CS0
R8
10K
/E5_CS1
R9
10K
/E5_CS2
R12
10K
4
E5_GPIO0
R13
10K
E5_GPIO1
R14
10K
E5_GPIO2
R15
10K
E5_GPIO3
R16
*10K
E5_GPIO4
R18
10K
E5_GPIO5
R22
10K
/WAIT
R25
10K
(FP D_HOST)
(/RST_PHY)
(/ETHER_IRQ)
E5_UART2_TX
1
TX1
(RST_CS4360)
(AUDIO_SEL0)
(AUDIO_SEL1)
E5_UART2_RX
1
RX1
1.8V
V18_E5_DAC_DVDD
E5_VCORE
FB1
3
V18
601
CA1
C3
+
T47u/16
104
GND
HD[15..0]
2.5V
V25
SSTL2_VDD
3.3V
L1
601
V33_E5_USB
E5_VDDX
L2
601
E5_AVDD
L3
601
E5_VDDREF
L4
601
V33_E5_DAC_AVDD
E5_VPAD
2
V33
C5
C4
+
104
T47u/16
GND
5V
VCC
E5_V5BIAS
1
LSI Logic Corp
Title
E5.1
Size
Document Number
Rev
HDW-10-310000-1
A1
Date:
Monday, June 07, 2004
Sheet
2
of
12
E
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