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Related Manuals for Mesa 7I43
Summary of Contents for Mesa 7I43
- Page 1 7I43/7I43H MANUAL V3.0...
- Page 2 This page intentionally not blank...
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Page 3: Table Of Contents
Table of Contents GENERAL ............1 DESCRIPTION . - Page 4 Table of Contents SUPPLIED CONFIGURATIONS ........19 EPPIOPR8 .
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Page 5: General
GENERAL DESCRIPTION The 7I43 is a USB/EPP version of the FPGA based Anything I/O card series. It provides 48 programmable I/O bits The 7I43H variant is a high speed USB version. Initial FPGA configurations can be downloaded to the 7I43 via the USB (7I43 and 7I43H) or EPP (7I43 only) port. -
Page 6: Hardware Configuration
The 7I43 can be powered by the USB host. The maximum power that can be supplied by a USB host is 450 mA. This will be sufficient for most but not all 7I43 applications. For applications that require more than the 450 mA supplied by the host, the 7I43 has provisions for external power. -
Page 7: Connector Power
4V in 3.3V mode. PRE-CONFIGURATION PULL-UPS The 7I43 has no pull-up resistors on its user I/O pins. This means that before these pins are configured, they will not have a defined state. If this is not desired, internal pull-up resistors on all FPGA pins can be enabled via Jumper W3. -
Page 8: Connectors
CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 7I43-U shown -P version has different defaults 7I43 4... - Page 9 CONNECTORS 7I43H CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 7I43 5...
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Page 10: I/O Connectors
P3 and P4 are the 7I43s I/O connectors. These are 50 pin box headers that mate with standard 50 conductor female IDC connectors. For information on which I/O pin connects to which FPGA pin, please see the 7I43IO.PIN file on the 7I43 distribution disk. 7I43 IO connector pinouts are as follows:... - Page 11 CONNECTORS 7I43 I/O CONNECTORS P3 CONNECTOR PINOUT FUNC FUNC FUNC FUNC IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38 IO39 IO40 IO41 IO42 IO43 IO44 IO45 IO46 IO47 POWER 7I43 7...
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Page 12: Jtag Connector
7I43 in EPP, standalone, and USB applications where USB host power is not sufficient to power the 7I43. On 7I43 card with revisions B or less, P1 is a four pin .1" male header. On 7I43s with revision C or greater or 7I43Hs’, P1 is a 2 pin 3.5MM pluggable screw terminal block. -
Page 13: Epp Interface Connector
CONNECTORS EPP INTERFACE CONNECTOR On the 7I43 (but not the 7I43H), P2 is the EPP printer port interface connector. P2 is a 26 pin header. P2 pin-out matches stands DB25 printer port pin-out, allowing a simple flat cable with a DB25M IDC connector on one end and a 26 pin female header on the other end to interface the hosts printer port to the 7I43. -
Page 14: Operation
PN XC3S200-5PQ144C or XC3S400-5PQ144C depending on 7I43 model. HOST INTERFACE The 7I43 uses either a USB or EPP printer port interface to the host. The 7I43H is USB only. These interfaces can be used for programming the FPGA and accessing the FPGA once programmed. -
Page 15: Usb Configuration
The CPLD also will echo characters to indicate the FPGA size and DONE status. If a character is sent to the 7I43 and the characters LSb is ‘1' the DONE status will be returned in the echoed characters LSb. If a character with a ‘0' LSb is sent, a character will be echoed indicating the FPGA size. -
Page 16: Eeprom Configuration
For stand-alone applications and when it is not desired to have to preconfigure the FPGA via the host interface at power up, the 7I43 can be configured via its serial EEPROM. Of course the Serial EEPROM must first be programmed with the desired configuration file. -
Page 17: Reconfiguration
FPGA without cycling the power, the FPGA configuration must include some way of asserting /RECONFIG. /RECONFIG is FPGA pin 52 on the 7I43 and pin 44 on the 7I43H. Note that pin 52 is also USB2CLK input on the 7I43H. This means that you should not load a standard 7I43/7I43H to a configuration file to a 7I43H and configure the USB chip for synchronous operation, not only will it not work, it will cause a bus conflict. -
Page 18: Clock Signals
OPERATION CLOCK SIGNALS The 7I43 has a 50 MHz crystal controlled clock signal routed to pin 53 (GCLK3) on the FPGA. Four user I/O pins are also GCLK pins: IO BIT GCLK FPGA PIN IO BIT GCLK FPGA PIN IOBIT0... -
Page 19: Usb-Fpga Interface
The 7I43H uses a FT2232H high speed USB interface chip (480 Mbps). Unlike the FT245R used in the 7I43, the FT2232H appears as two serial ports. Only the first port is used by the 7I43H. The supplied configurations support the same FIFO interface mode as... -
Page 20: Additional 7I43H Interface Pins
SPI CHIP SELECT LEDS The 7I43 has 8 FPGA driven user LEDS. These green LEDS are located in the top center of the card. They can be used for any purpose, and can be helpful as a simple debugging feature. A low output signal from the FPGA lights the LED. -
Page 21: Bus Switch Mode
The 7I43 uses bus switch devices in series with all I/O pins. These devices allow the 7I43 inputs to be 5V tolerant and allow the I/O pins to be pulled up to 5V. The bus switch input protection function works by disconnecting the FPGA from the IO pins when the IO pin voltage rises above a preset threshold. -
Page 22: Startup I/O State
5V tolerance, and the output should be driven in open drain mode. This is because the 7I43 outputs only swing to 3.3V in normal mode, leaving 1.7V (5V -3.3V) driving the SSR when the output is high and the SSR should be off. -
Page 23: Supplied Configurations
The GPIO is organized as six eight bit ports, each with an associated Data Direction Register (DDR).The EPPIOPR8 configuration can be used as a starting point for more complicated user configurations. There are two EPPIOPR8 configuration files, EPPIO8-2.BIT for the 200K and EPPIO8-4.BIT for 400K versions of the 7I43. PORT DATA REG... -
Page 24: Usbiopr8
Little Binary Protocol (LBP) is used to communicate with standard addressable peripherals in the 7I43 FPGA configuration. The GPIO is organized as six eight bit ports, each with an associated Data Direction Register (DDR).The USBIOPR8 configuration can be used as a starting point for more complicated user configurations. -
Page 25: Lbp
LBP is a simple master slave protocol where the host sends read, write, or RPC commands to the 7I43, and the 7I43 responds. LBP allows the host (master) to efficiently access registers on the slave (7I43) via a simple bidirectional byte oriented protocol. -
Page 26: Example Commands
Write 2 more bytes (0xEE,0xFF) at 0x014 and 0x015: COMMAND BITS LBPWrite: 0 add 2 data Write data 0 Write data 1 Read 8 bytes at 0x010,0x011,0x012,0x013,0x014,0x015,0x016,0x017: COMMAND BITS LBPRead: 2 add 8 data Read Address LSB Read Address MSB 7I43 22... -
Page 27: Local Lbp Commands
0xC3 Get CRC error count 0xC4 .. 0xC9 Reserved 0xCA Get Enable_RPCMEM access flag 0xCB Get Command timeout (in mS for USB and character times/10 for serial) 0xCC Get Non-volatile memory flag 0xCD Get External memory flag 0xCE.. 0xCF Reserved 7I43 23... - Page 28 0xDA Get LBP version 0xDB Get LBP Unit ID (Serial only, not used with USB) 0xDC Get RPC Pitch 0xDD Get RPC SizeL (Low byte of RPCSize) 0xDE Get RPC SizeH (High byte of RPCSize) 0xDF Get LBP cookie (returns 0x5A) 7I43 24...
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Page 29: Local Lbp Write Commands
0xF8 Set low address 0xF9 Set high address 0xFA Add byte to current address 0xFB .. 0xFC Reserved 0xFD Set unit ID (serial only) 0xFE Reset LBP processor if followed by 0x5A 0xFF Reset LBP parser (no data follows this command) 7I43 25... -
Page 30: Rpc Commands
RPCPitch of 0x10 bytes, RPC0 starts at 0x0000, RPC1 starts at 0x0010, RPC2 starts at 0x0020 and so on. Before RPC commands can be written to the RPC table, the RPCMEM access flag must be set. The RPCMEM access flag must be clear for normal operation. 7I43 26... -
Page 31: Example Rpc Command List
LBPWrite 2 add 1 data Write Address LSB Write Address MSB Write Data Terminator The data stream for this RPC would consist of these 3 bytes: COMMAND BITS RPC 5 Data 0 for Command 1 Data 1 for Command 1 7I43 27... -
Page 32: Available Daughter Cards
6 channel analog servo interface 7I49 6 channel resolver interface 7I50 SPI I/O expander 7I64 24 input, 24 output isolated I/O 7I65 Octal16 bit A-D analog servo interface 7I66-8 16 input 8 output isolated I/O 7I66-24 24 output isolated I/O 7I43 28... -
Page 33: Reference Information
FPGA configuration MAXIMUM I/O I SINK OR I SOURCE ---- 24mA MAXIMUM I/O INPUT VOLTAGE -.5V 5.5V 5V Tolerant mode. I/O 0..47, EPP I/O MAXIMUM I/O INPUT VOLTAGE -.5V 3.3V mode. I/O 0..47 TEMPERATURE -C VERSION TEMPERATURE -I VERSION 7I43 29...
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