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AT INTERFACE and ATA COMMANDS
6-3-3-2
Drive Address Register (3F7h)
This register contains the inverted drive select and head select addresses of the currently
selected drive. The bits in this register are as follows:
7
6
HiZ
nWTG
• HiZ is always in a high impedance state.
• nWTG is the Write Gate bit. When writing to the disk drive is in progress, nWTG=0.
• nHS3 through nHS0 are the one's complement of the binary coded address of the
currently selected head. For example, if nHS3 through nHS0 are 1100b, respectively,
head 3 is selected. nHS3 is the most significant bit.
• nDS1 is the drive select bit for drive 1. When drive 1 is selected and active, nDS1=0.
• nDS0 is the drive select bit for drive 0. When drive 0 is selected and active, nDS0=0.
NOTE : Caching, translation and master/slave may cause this register to contain invalid
data.
6-3-3-3
Device Control Register (3F6h)
The bits in this register are as follows:
7
6
X
X
• SRST is the host software reset bit. The drive is held reset when this bit is set. If two
disk drives are daisy chained on the interface, this bit resets both simultaneously.
• nIEN is the enable bit for the drive interrupt to the host. When nIEN=0, and the
drive is selected, INTRQ is enabled through a tri-state buffer. When nIEN=1, or the
drive is not selected, the INTRQ signal is in a high impedance state.
6-3-4
Command Block Register Descriptions
6-3-4-1
Data Register (1F0h)
This 16-bit register is used to transfer data blocks between the device data buffer and the
host. It is also the register through which sector information is transferred on a Format
Track command. Data transfers may be either PIO or DMA.
6-
12 WA31273A / WA32543A / WA33203A / WA3216A / WA31083A / WA32162A
5
4
3
nHS3
nHS2
5
4
X
X
2
1
nHS1
nHS0
3
2
1
SRST
0
nDS1
nDS0
1
0
nIEN
0
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