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Philips Semiconductors
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
X1/CLK
DTACKN
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
X1/CLK
A1–A4
D0–D7
DTACKN
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
NOTE:
For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and
registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.
2004 Oct 21
t
CSC
t
AS
A1–A4
t
CS
RWN
t
CSN
AH
t
DD
NOT
D0–D7
VALID
t
DA
Figure 6. Bus Timing (Read Cycle) (68XXX mode)
t
CSC
t
AS
t
CS
RWN
t
CSN
AH
t
DS
Figure 7. Bus Timing (Write Cycle) (68XXX mode)
t
CH
t
RWD
t
DF
DATA VALID
t
DAH
t
DCR
t
DAT
SD00687
t
CH
t
RWD
t
DH
t
t
DAH
DCW
t
DAT
SD00688
34
Product data sheet
SC28L91
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