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Philips Semiconductors
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
Register Acronyms and Read / Write Capability
(R/W = Read/Write, R = Read only, W = Write only)
Mode Register
Status Register
Clock Select
Command Register
Receiver FIFO
Transmitter FIFO
Input Port Change Register
Auxiliary Control Register
Interrupt Status Register
Table 2. Condensed Register bit formats
ame
Adr
Bit 7
N
MR0
0
WATCH
DOG
MR1
0
RxRTS
Control
MR2
0
Channel Mode
CSR
1
Receiver Clock, Select Code
SR
1
Received
Break
CR
2
Channel Command codes
RxFIFO
3
Read 8 bits from Rx FIFO
TxFIFO
3
Write 8 bits to Tx FIFO
IPCR
4
Delta IP3
ACR
4
Baud Group Counter Timer mode and clock select
ISR
5
Change
Input Port
IMR
5
Change
Input Port
CTU
6
Read 8 MSb of the BRG Timer divisor.
CTPU
6
Write 8 MSb of the BRG Timer divisor.
CTL
7
Read 8 LSb of the BRG Timer divisor.
CTPL
7
Write 8 LSb of the BRG Timer divisor.
IPR
D
State of IP
OPCR
D
Configure
OP7
Strt C/T
E
Read Address E to start Counter Timer
SOPR
E
Set OP 7
Stp C/T
F
Read Address F to stop counter Timer
ROPR
F
Reset OP 7
2004 Oct 21
MRn
R/W
SR
R
CSR
W
CR
W
RxFIFO
R
RxFIFO
W
IPCR
R
ACR
W
ISR
R
Bit 6
Bit 5
Bit 4
RxINT BIT 2
TxINT [1:0]
RxINT BIT 1
Error Mode
Parity Mode
TxRTS
CTSN Enable
Control
Tx
Framing
Parity Error
Overrun Error
Error
Delta IP2
Delta IP1
Delta IP0
Ignore in ISR Reads
Set to 0
Set to 0
Set to 0
State of IP 6
State of IP 5
State of IP 4
Configure
Configure
Configure
OP6
OP5
OP4
Set OP 6
Set OP 5
Set OP 4
Reset OP 6
Reset OP 5
Reset OP 4
Interrupt Mask Register
Counter Timer Upper Value
Counter Timer Lower Value
Counter Timer Preset Upper
Counter Timer Preset Lower
Input Port Register
Output Configuration Register
Set Output Port
Reset Output Port
Interrupt vector or GP register
Bit 3
Bit 2
FIFO SIZE
BAUD RATE
EXTENDED
II
Parity Type
Stop Bit Length
Transmitter Clock select code,
TxEMT
TxRDY
Disable Tx
Enable Tx
State of IP3
State of IP2
Enable IP3
Enable IP2
Counter
Change
Ready
Break
Counter
Change
Ready
Break
State of IP 3
State of IP 2
Configure OP3
Set OP 3
Set OP 2
Reset OP 3
Reset OP 2
21
Product data sheet
SC28L91
IMR
W
CTU
R
CTL
R
CTPU
W
CTPL
W
IPR
R
OPCR
W
Bits
W
Bits
W
IVR/GP
R/W
Bit 1
Bit 0
TEST 2
BAUD RATE
EXTENDED 1
Bits per Character
RxFULL
RxRDY
Disable Rx
Enable Rx
State of IP1
State of IP0
Enable IP1
Enable IP0
RxRDY
TxRDY
RxRDY
TxRDY
State of IP1
State of IP 0
Configure OP2
Set OP 1
Set OP 0
Reset OP 1
Reset OP 0
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