Table of Contents
Advertisement
3. TECHNICAL BRIEF
VBAT
2V8_VEXT
U201
MIC2211-GMYML
1
VIN
VOUT1
2
EN1
VOUT2
3
EN2
NC3
4
BYP
NC2
C205
C206
GND
1u
27p
5
C207
NC1
BGND
0.01u
(GPIO_12)
MIDI_RST
26MHZ
1V8_MIDI
2V8_MIDI
C219
C222
0.1u
1u
C220
0.1u
CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/WR,/RD,/CS,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ),
totaling 13 pins are connected to the external CPU. This block controls the writing and
reading of data by the input polarity of control signal
INTERFACE REGISTER
These registers are able to access directly from the external CPU. There are 2 bytes spaces. The
Intermediate register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register. This
register is called "Intermediate register" since this exists in the middle of the interface register and the
Control register.
In the Intermediate register, there are some registers to control various functions.
64POLY MIDI
1V8_MIDI
2V8_MIDI
R220
R221
0
0
10
9
8
7
6
11
C208
C209
1u
10u
B4
_RST
C211
G5
CLKI
1000p
D2
BLCK
D3
LRCK
D1
SDI
D6
GPIO0
C5
GPIO1
C1
GPIO2
C4
GPIO3
B1
LED2_GPIO5
C2
LDE1_GPIO4
VBAT
C3
LED0
B2
MTR
FB201
C223
1u
C226
C227
C221
C228
22u
1u
0.1u
27p
Figure 3-28. YMU787 CIRCUIT DIAGRAM
120p
C201
C203
R204
0.1u
1000p
30K
C202
22n
C204
SPOUT2L
SPOUT1L
SPOUT2R
SPOUT1R
U204
YMU787
EXTOUT
HPOUTL
HPOUTR
C224
C225
0.1u
1u
- 60 -
SPK_P_SM
B8
MIDI_SPK-
B7
C212
NA
H8
J8
E8
TXOUT
MIDI_SPK+
D7
G7
EXC
E6
BBL
C8
MIDI_HPLOUT
E7
BBR
C7
MIDI_HPROUT
C216
C217
C218
0.1u
0.1u
1u
Advertisement
Table of Contents
