Analog Assembly - Datron 1062 Service Handbook

17
Secondly, the
latches of
the
D
-
A
converter (M13,
M14)
are
set
up
with the input
bias
current
(lb)
compensation
data.
The
ID
lines
are set to the appropriate pattern and
the
information
is
clocked on
to
M13
and
M14
by
a
delayed
low
to high edge
from Ml
7-4,
originating
from
I
A0
going
low.
The
delay
makes
sure that the
signal
from
Ml
7-10
has disabled
the
"F.E.T."
latch
M21. Once
again, the
IA0
line returns to the resting state of
logic
'1'. Thirdly,
the
DC
analog
circuits are enabled by
setting
all
the ID
lines
high except
for IDO, then clocking
M20
by
a
low
to high
edge from
Ml
6-6 caused by both
I
A
lines
going low.
Once DC
has been
selected,
the F.E.T. pattern
latch
is
enabled from M12-1, and
the
penultimate
step
is
to load
this latch with
1000V
range data
from
the ID
lines
(ID4
low, the
rest high).
This
is
executed by
clocking the 'F.E.T.'
latch
from
Ml
7-4
once
again,
but
this
time being due
to
IA1 going
low.
The
final
step
is
to reselect
DC
as
described
above.
3. 2.1.
3 General
Interface
Update Sequence
Before the
start
of each reading, the analog
interface
undergoes
a
complete
update.
The
series
of events
is
the
same
as
the power-up sequence
for selection
of function
and
range,
as
can be seen by comparing
the
two
flowcharts
(Figs. 3.3
and
3.5).
When Ohms
or Current
is
selected,
the
DC
Isolator or
AC
assembly
is
also
used
in
the
measure-
ment
procedure
as
seen
in
the following
table.
^
Type
of
Measurement
Circuits Selected Use of
D
-
A
DC
Volts Analog Assembly
Input Bias Current
Compensation
AC
Volts
AC
Assembly Frequency Compensation
AC
-H
DC
Volts
AC
Assembly Frequency Compensation
Resistance
Ohms
Assembly
and
Analog Assembly
Input
Bias Current
Compensation
DC
Current
Current
Assembly
and
Analog Assembly
Input
Bias
Current
Compensation
AC
Current Current Assembly
and
AC
Assembly
Frequency Compensation
AC
-1-
DC
Current Current Assembly
and
AC
Assembly
Frequency Compensation
The
update sequence
order
is (i)
Deselect
all
assemblies,
(ii)
Load
D
-
A
latches,
(iii)
Select
AC
assembly
or
DC
Isolator,
(iv)
Load
range
pattern into
DC
or
AC
range
latches,
(v)
Deselect
DC
or
AC
and
select either the
Ohms
or Current assembly,
(vi)
Load
range pattern
into
f2's
or
I
range
latches,
(vii)
Reselect
circuits selected
in
(iii)
and
(iv).
Note: Steps
(v)
and
(vi)
are
used only when
I
or
12
is
selected.
/
\
FIG.
3.5
ANALOG
INTERFACE
SEQUENCE:
OHMS
SELECT
Flowchart
3.5 gives
the above sequence
for an
ohms
update.
The
general
form
of the timing diagram
for the
above sequence
is
given
in
Fig.
3.6,
the analog
'F.E.T.'
patterns for each range
of each function being
given
in
Appendix
1.
3.2. 1.4 Test
When TEST
is
selected, a logic
'0'
is
placed
on ID7
at stages
(iii), (v)
and
(vii) in
Fig. 3.6,
i.e.
each time
a
func-
tion
measurement
circuit
is
selected.
Appendix
1
lists
the
'F.E.T.' patterns of each assembly
for
each
test
measurement
cycle.
3.2.2
DC
Isolator
Section
3.2.2.1 Preamplifier Scaling (430328
sheet
1
Figure 3.8
shows
the
essential features of the
iso-
lator scaling circuit.
For
the
purpose
of explanation the
same symbols
are used, regardless of whether
the switching
is
accomplished
electronically (F.E.T.) or
by means
of
relay
contacts.
In
Fig. 3.8
all
switches
are
shown
in
the
IV
RANGE
position.