Texas Instruments TAS2505 Reference Manual
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Texas Instruments TAS2505 Reference Manual

Texas Instruments TAS2505 Reference Manual

Low power digital input speaker amp with support for 24-bit digital i2s data mono playback
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TAS2505 Application Reference Guide
Reference Guide
Literature Number: SLAU472
February 2013

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Summary of Contents for Texas Instruments TAS2505

  • Page 1 TAS2505 Application Reference Guide Reference Guide Literature Number: SLAU472 February 2013...
  • Page 2 – Digital I/O: 1.1 V–3.6 V – Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD) • 4mm × 4mm 24-Pin QFN Package C is a trademark of NXP B.V. Corporation. TAS2505 Device Overview SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 3 Description The TAS2505 is a low power digital input speaker amp with support for 24-bit digital I2S data mono playback. In addition to driving a speaker amp upto 4-Ω, the device also features a mono headphone driver and a programmable digital-signal processing block.
  • Page 4 47PF AINL AINR 0.1PF Analog Input MISO SCLK SPI_SEL DVDD DVSS IOVDD IOVSS +1.8VD IOVDD 10PF 0.1PF 10PF 0.1PF Figure 1-2. Typical Circuit Configuration TAS2505 Device Overview SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 5 Headphone jack HPOUT 0.1PF 47PF AINL AINR 0.1PF Analog Input MISO SCLK SPI_SEL IOVDD IOVSS IOVDD 0.1PF 10PF Figure 1-3. Application Schematics for LDO SLAU472 – February 2013 TAS2505 Device Overview Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 6 E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.) TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 7 Secondary I S WCLK input Secondary I S DIN Secondary I S BCLK OUT Secondary I S WCLK OUT Secondary I S DOUT Aux Clock Output SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 8 S DIN on DIN D2-D1 = 01 on GPIO/DOUT D5-D2 = 1001 Secondary I S WCLK OUT Page 0, Register 55, Bits on MISO D4-D1 = 1010 TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...

  • Page 9: Analog Signals

    2.4.1 DAC The TAS2505 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the mono DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter.
  • Page 10 The DAC path of the TAS2505 features many options for signal conditioning and signal routing: • Digital volume control with a range of -63.5 to +24dB • Mute function In addition to the standard set of DAC features the TAS2505 also offers the following special features: • Digital auto mute • Adaptive filter mode 2.4.1.1...
  • Page 11 However, the TAS2505 offers an adaptive filter mode as well. Setting page 8, register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients can be updated through the host and activated without stopping and restarting the DAC.
  • Page 12 0x000000 C8 (Page 44, registers 40, 41, 42) 0x000000 C9 (Page 44, registers 44, 45, 46) 0x000000 C10 (Page 44, registers 48, 49, 50) 0x000000 TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 13 Condition Value (Typical) Unit Filter-gain pass band 0 … 0.45 f ±0.015 Filter-gain stop band 0.55 f … 7.455 f –65 Filter group delay 21/f SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 14 (Red Line Corresponds to –58 dB) –10 –20 –30 –40 –50 –60 –70 –80 Frequency Normalized to f Figure 2-4. Frequency Response of Channel Interpolation Filter B TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 15 This avoids polling the status-flag registers continuously. The TAS2505 has two defined interrupts, INT1 and INT2, that can be configured by programming page 0, register 48 and page 0, register 49. A user can configure interrupts INT1 and INT2 to be triggered by one or many events, such as: •...
  • Page 16 DAC filter coefficient values is not permitted. (The DAC should not be powered up until after all of the DAC configurations have been done by the system microprocessor.) TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 17 Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 2-5. Example Flow For Updating DAC Digital Filter Coefficients During Play SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 18 2.4.7 Analog Audio Routing The TAS2505 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels.

  • Page 19: Analog Outputs

    The analog volume-control soft-stepping time is based on the setting in page 0, register 63, bits D1–D0. 2.4.8 Analog Outputs Various analog routings are supported for playback. All the options can be viewed in the functional block diagram, Figure 2-6. SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 20 2.4.8.1 Headphone Drivers The TAS2505 features a mono headphone driver (HPOUT) that can deliver up to 28 mW channel, at 1.8-V supply voltage, into a 16-Ω load. The headphones are used in a single-ended configuration where an ac- coupling (dc-blocking) capacitor is connected between the device output pins and the headphones. The headphone driver also supports 32-Ω...
  • Page 21 To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD voltage level. The TAS2505 has a thermal protection (OTP) feature for the speaker driver which is always enabled to provide protection. If the device is overheated, then the output stops switching. When the device cools down, the output resumes switching.
  • Page 22 2.4.10 5V LDO The TAS2505 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply (DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is 50 mA or less, then this LDO can deliver power to both analog and digital power supplies.
  • Page 23 Audio DAC and Audio Analog Outputs www.ti.com 2.4.11 POR TAS2505 has a POR (Power On Reset) function as shown Figure 2-7. This function insures that all registers are automatically set to defaults when a proper power up sequence is executed. The function consume approximately 35uA from the DVDD so if needed this can be disabled by page 1, register 1, bit D3 = 1.
  • Page 24 (e) Program OSR value (f) Program I2S word length if required (16, 20, 24, or 32 bits) (g) Program the processing block to be used TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 25 The choice of processing blocks, PRB_P1 to PRB_P3 for playback, also influences the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice between power-optimization and configurations with more signal-processing resources. SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 26 Alternative Processing Blocks: Processing Block Filter Estiamted Power Change at PTM_P1 HP out Unit CM = 0.75V CM = 0.9V PRB_P1 +1.46 +1.49 PRB_P2 0.00 +0.03 TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 27 Alternative Processing Blocks: Processing Block Filter Estiamted Power Change at PTM_P1 HP out Unit CM = 0.75V CM = 0.9V PRB_P1 +0.43 +0.43 PRB_P3 +0.17 +0.18 SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 28 2.5.3 Speaker output Power Consumption To consider Speaker output power consumption on the TAS2505, the tables in this section to be may useful to know the power consumption for each power rail. The tables shows selected as representable combination of PRB mode and PTM mode.
  • Page 29 2.5.4 Headphone output Power Consumption To consider Headphone output power consumption on the TAS2505, the tables in this section to be may useful to know the power consumption for each power rail. The tables shows selected as representable combination of PRB mode and PTM mode.

  • Page 30: Clock Generation And Pll

    CLOCK Generation and PLL The TAS2505 supports a wide range of options for generating clocks for the DAC sections as well as interface and other control blocks as shown in . The clocks for the DAC require a source reference clock.
  • Page 31 Figure 2-9. BCLK Output Options In the mode when TAS2505 is configured to drive the BCLK pin (page 0, register 27, bit D3 = 1), it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0, register 30, bits D6–D0 from 1 to 128 (see...
  • Page 32 When the input MCLK or other source clock is not an integer multiple of the audio processing clocks, then it is necessary to use the on-board PLL. The TAS2505 fractional PLL can be used to generate an internal master clock used to produce the processing clocks needed by the DAC and Digital Effects.
  • Page 33 BCLK input, GPIO input or PLL_CLK (Page 0, Register 4, Bit D1 to D0) ). If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last. SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...

  • Page 34: Digital Audio Interface

    The TAS2505 also includes a feature to offset the position of start of data transfer with respect to the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page 0, register 28.
  • Page 35 Digital Audio and Control Interface www.ti.com By default, when the word clocks and bit clocks are generated by the TAS2505, these clocks are active only when the DAC is powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit clocks can be active even when the codec in the device is powered down.
  • Page 36 Left-Justified Mode The audio interface of the TAS2505 can be put into left-justified mode by programming page 0, register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock.
  • Page 37 DSP Mode The audio interface of the TAS2505 can be put into DSP mode by programming page 0, register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data.
  • Page 38 Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data. TAS2505 Application SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 39 Primary and Secondary Digital Audio Interface Selection The audio serial interface on the TAS2505 has I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections.
  • Page 40 START condition is issued while the bus is active, it is called a repeated START condition. The TAS2505 can also respond to and acknowledge a general call, which consists of the master issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be enabled via page 0, register 34, bit D5.
  • Page 41 MISO pin to the master shif tregister. The TAS2505 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge.

  • Page 42: Power Supply

    Figure 2-25. SPI Timing Diagram for Register Read Power Supply The TAS2505 integrates a large amount of digital and analog functionality, and each of these blocks can be powered separately to enable the system to select appropriate power supplies for desired performance and power consumption.

  • Page 43: System Level Considerations

    This state results in standby current of approximately 1.5μA from the AVDD supply. In standby mode the device responds very quickly to playback requests. SLAU472 – February 2013 TAS2505 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 44 Device Special Functions 2.9.1 Interrupts Some specific events in the TAS2505 which may require host processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TAS2505 has two defined interrupts; INT1 and INT2 that can be configured by programming Page 0, Register 48 and 49.

  • Page 45: Device Initialization

    Example device setups are described in the next chapter. Power On Sequence There are two recommended power sequence possible for TAS2505: 1. Speaker Supplies, then Digital Supplies, then Analog Supplies 2. Speaker Supplies, then Digital and Analog Supplies The first power on sequence is useful if the end system uses separate analog and digital supplies.
  • Page 46 Figure 3-2. Digital and Analog 1.8 V Supplies provided Together After RST is released (or a software reset is performed), no register writes should be performed within 1 Device Initialization SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 47 Device Initialization 3.2.1 Reset by RST pin and POR The TAS2505 internal logic must be initialized to a known condition for proper device function. This can be accomplished in two ways: 1. The first way is to take no action and let the internal POR circuit that detects the minimum DVDD and IOVDD levels automatically reset the device into its default condition.
  • Page 48 3.2.6 Device Common Mode Voltage The TAS2505 allows the user to set the common mode voltage for analog inputs to 0.75V or 0.9V by programming Page 1, Register 10, D(6). The input common-mode voltage of 0.9V works best when the analog supply voltage is centered around 1.8V or above, and offers the highest possible performance.

  • Page 49: Example Setups

    Example Setups The following example EVM I C register control scripts can be taken directly for the TAS2505 EVM setup. The # marks a comment line, w marks an I2C write command followed by the device address, the I2C register address and the value. The EVM I...
  • Page 50 # Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7- D6=00, D5-D4=00, D3-D2=00) W 30 1B 00 # Data slot offset 00 (P0, R28, D7-D0=0000) W 30 1C 00 Example Setups SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 51 # Enable AINL and AINR and Power up HP (P1, R9, D5=1, D1-D0=11) w 30 09 23 # Unmute HP with 0dB gain (P1, R16, D4=1) w 30 10 00 SLAU472 – February 2013 Example Setups Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 52 # LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0) W 30 02 00 # Page switch to Page 0 Example Setups SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 53 30 2C 7E 7A 4F # reg 48/49/50 - D2 Coefficient w 30 30 80 74 84 #----------------------------------------------------------------------- BQ-C = 5 KHz Notch BW = 125 #----------------------------------------------------------------------- SLAU472 – February 2013 Example Setups Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 54 W 30 00 00 # Assert Software reset (P0, R1, D0=1) W 30 01 01 # Page Switch to Page 1 W 30 00 01 Example Setups SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 55 # reg 24/25/26 - D1 Coefficient w 30 18 7F 72 C7 # reg 28/29/30 - D2 Coefficient w 30 1C 80 74 84 #----------------------------------------------------------------------- SLAU472 – February 2013 Example Setups Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 56 #----------------------------------------------------------------------- # reg 92/93/94 - N0 Coefficient w 30 5C 7F C5 BD # reg 96/97/98 - N1 Coefficient w 30 60 94 6B EF Example Setups SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 57 # DAC digital gain 0dB (P0, R65, D7-D0=00000000) W 30 41 00 # DAC volume not muted. (P0, R64, D3=0, D2=1) W 30 40 04 SLAU472 – February 2013 Example Setups Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...

  • Page 58: Register Map

    RST. Page control is done by writing a new page value into register 0 of the current page. The control registers for the TAS2505 are described in detail as follows. All registers are 8 bits in width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
  • Page 59 0001: PLL multiplier R = 1 0010: PLL multiplier R = 2 0011: PLL multipler R = 3 0100: PLL multipler R = 4 0101…0111: Reserved. Do not use SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 60 000 0000: NDAC=128 000 0001: NDAC=1 000 0010: NDAC=2 … 111 1110: NDAC=126 111 1111: NDAC=127 Note: Please check the clock frequency requirements in the Overview section. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 61 CDIV_CLKIN Clock Selection 000: CDIV_CLKIN = MCLK 001: CDIV_CLKIN = BCLK 010: CDIV_CLKIN = DIN 011: CDIV_CLKIN = PLL_CLK 100: CDIV_CLKIN = DAC_CLK 101: CDIV_CLKIN = DAC_MOD_CLK SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 62 1: Priamry BCLK and Primary WCLK buffers are powered down when the codec is powered down D1–D0 BDIV_CLKIN Multiplexer Control 00: BDIV_CLKIN = DAC_CLK 01: BDIV_CLKIN = DAC_MOD_CLK 10: Do not use 11: Do not use Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 63 Reserved. Write only default values. Audio Data In Control 0: DIN is used for Audio Data In 1: Secondary Data In is used for Audio Data In SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 64 0: Gain applied in DAC PGA is not equal to Gain programmed in Control Register 1: Gain applied in DAC PGA is equal to Gain programmed in Control Register" D3–D0 0000 Reserved. Write only zeros to these bits. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 65 Reserved. Write only default value. Page 0 / Register 47: Reserved - 0x00 / 0x2F Read/Write Reset Value DESCRIPTION D7-D0 0000 0000 Reserved. Write only default value. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 66 GPIO as general purpose output control 0: GPIO pin is driven to '0' in general purpose output mode 1: GPIO pin is driven to '1' in general purpose output mode Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 67 Secondary Data Input or Secondary Bit Clock Input or Secondary Word Clock. 10: SCLK is enabled as General Purpose Input 11: Reserved. Do not use Value of SCLK input pin when used as General Purpose Input SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 68 111: DAC is auto muted if input data is DC for more than 6400 consecutive inputs DAC Channel Mute Control 0: DAC Channel not muted 1: DAC Channel muted Reserved. Write only default value. D1-D0 Reserved. Write only default values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 69 Page 0 / Register 82 - 127 Reserved Registers - 0x00 / 0x520x7F Read/Write Reset Value DESCRIPTION D7–D0 0000 0000 Reserved. Write only default values. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 70 000: DAC in mode PTM_P3, PTM_P4 001: DAC in mode PTM_P2 010: DAC in mode PTM_P1 011-111: Reserved. Do not use D1-–0 Reserved. Write only default values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 71 0: Output current will be limited if over current condition is detected 1: Output driver will be powered down if over current condition is detected SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 72 Page 1 / Register 17 - 19: Reserved - 0x01 / 0x11 - 0x13 Read/Write Reset Value Description D7 -D0 0000 0000 Reserved. Write only default values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 73 11: Reserved. Do not use Page 1 / Register 21: Reserved - 0x01 / 0x15 Read/Write Reset Value Description D7-D0 0000 0000 Reserved. Write only default values. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 74 111 0100: Volume Control = -72.3dB 110 1100: Volume Control = -55.4dB 111 0101: Volume Control = Mute 111 0110-111 1111: Reserved. Do not use Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 75 TAS2505 Register Map www.ti.com Page 1 / Register 23: Reserved - 0x01 / 0x17 Read/Write Reset Value Description D7-D0 0000 0000 Reserved. Write only default values. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 76 111 0100: Volume Control = -72.3dB 110 1100: Volume Control = -55.4dB 111 0101: Volume Control = Mute 111 0110-111 1111: Reserved. Do not use Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 77 111 0100: Volume Control = -72.3dB 110 1100: Volume Control = -55.4dB 111 0101: Volume Control = Mute 111 0110-111 1111: Reserved. Do not use SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 78 Reserved. Write only Reset Values. Speaker Driver Power 0: SPK output driver is powered down 1: SPK output driver is powered up Reserved. Write only default values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 79 110 1011: Volume Control = -54.2 dB 111 0100: Volume Control = -72.3 dB 110 1100: Volume Control = -55.4 dB 111 0101 - 1111110: Reserved 111 1111: Mute SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 80 Page 1 / Register 84 - 121: Reserved - 0x01 / 0x54 - 0x79 Read/Write Reset Value Description D7-D0 0000 0000 Reserved. Write only Reset Values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 81 Page 1 / Register 123 - 127: Reserved - 0x01 / 0x7A -0x7F Read/Write Reset Value Description D7-D0 0000 0000 Reserved. Write only Reset Values. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...

  • Page 82: Reserved Register

    DAC channel is powered down. Default values shown for this page only become valid 100 μs following a hardware or software reset. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 83 DAC channel is powered down. Default values shown for this page only become valid 100 μs following a hardware or software reset. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 84 Pages 71 – 255 / Register 0 - 127 : Reserved - 0x47 - 0xFF / 0x00 -0x7F Read/Write Reset Value DESCRIPTION D7–D0 XXXX XXXX Reserved Register. Don't write any values. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 85 C209 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C239 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C255 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 86 C209 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C239 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C255 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Register Map SLAU472 – February 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 87 C44,..,C47 00000000H 7FFFFFFFH C49,..,C52 00000000H 7FFFFFFFH C54,..,C57 00000000H 7FFFFF00H C59,..,C64 00000000H 7FFFFFFFH C66,C67 00000000H 7FFFFFFFH C69,C70 00000000H 7FF70000H 10090000H 7FEF0000H C74,C75 00110000H 7FDE0000H C77,..,C255 00000000H SLAU472 – February 2013 Register Map Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...

  • Page 88: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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