Sharp ER-A57R1 Service Manual page 50

•
CLK
TC
TWH TWL
CLK
•
A8, A9, A10, A15 timings
Φ
AEN
AST
TSDG
D0-D7
A8, A9, A10, A15
•
MSK, RSO timings
Φ
DAK01
TTCG
TCH
TDMG
MSK
LCS
TTRG
RS0
RS1
•
TXC, TDI timings
Φ
TCTG T CT H
TXC
TTDG
TXD
TCIG
TDI
•
RXC, RXD timings
RXWS
RDI
T RX Y
T RX L T RX H
RXC
TR DS U T RD H
RXD
Fig. 15
TSDH
TADG
Fig. 16
T TC H
TDMH
: Duringtransfer
: Transfer and
T TR H
Fig. 17
TTDG
TCIH
Fig. 18
RXWL
Fig. 19
•
Collision generation time
RDI
TCOL
COL
4. Description of the DMA controller
(DMAC; µPD8257-2)
The µPD8257 DMAC is a signal-chip, programmable DMA controller
designed to control DMA transfers between the I/O devices and
memory. The following outlines the DMAC operations:
1) DMA Opretion
Data transfer between I/O devices and memory is normally done via
the CPU (see Fig. 21).
Memory
The memory contents are temporarily stored in the CPU's
internal register before being written into an I/O device at the next
step.
In contrast, the DMA controller allows data to be directly transferred
between memory and I/O devices without the CPU (See Fig. 22).
Control signal
Memory
The DMAC (8257) permits data transfers only between memory and
I/O devices. (Some type of DMACs allow data transfer between
memories).
4 ™ 7
TCOL
Fig. 20
CPU
I/O device
Fig. 21
Control signal
DMA C
I/O device
Data
Fig. 22