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Sharp ER-A57R1 Service Manual

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ER-A570 OPTION
I.
SRN (IN-LINE) SYSTEM FOR ER-A570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
II. RS-232 SYSTEM FOR ER-A570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
III. TEST FUNCTION FOR ER-A6IN AND ER-A5RS . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
IV. HARDWARE DESCRIPTION FOR ER-A6IN AND ER-A5RS . . . . . . . . . . . . . . . . . 4-1
PARTS GUIDE
Parts marked with "! " is important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
SERVICE MANUAL
MODEL
MODEL
MODEL
CONTENTS
SHARP CORPORATION
CODE: 00ZERA57VOSME
SRN (IN-LINE) INTERFACE
ER-A6IN
RS-232 INTERFACE
ER-A5RS
CONTROL ROM
ER-A57R1
(For "V" version)
This document has been published to be used for
after sales service only.
The contents are subject to change without notice.

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Summary of Contents for Sharp ER-A57R1

  • Page 1 RS-232 INTERFACE ER-A5RS MODEL CONTROL ROM ER-A57R1 MODEL (For "V" version) CONTENTS SRN (IN-LINE) SYSTEM FOR ER-A570 ....... . . 1-1 II.
  • Page 2 Precautions 1. Downloading the data from the ER-02FD in the inline system To download the data from the ER-02FD onto the ECR in the inline system, the following procedure must be observed. 1) Download the data from the ER-02FD onto the ECR using the SRV #998. 2) Execute the SRV RESET operation.
  • Page 3 CAUTION FOR BATTERY REPLACEMENT (Danish) ADVARSEL ! Lithiumbatteri – Eksplosionsfare ved fejlagtig håndtering. Udskiftning må kun ske med batteri af samme fabrikat og type. Levér det brugte batteri tilbage til leverandoren. (English) Caution ! Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the equipment manufacturer.

  • Page 4: Table Of Contents

    I. SRN (IN-LINE) SYSTEM FOR ER-A570 ER-A6IN ER-A57R1 (For ER-A570) MODEL (OPTIONS FOR ER-A570) CONTENTS CHAPTER 1. ER-A570 SRN (IN-LINE) SYSTEM CONFIGURATION ..1-2 CHAPTER 2. HARDWARE REQUIREMENTS ......1-2 CHAPTER 3.

  • Page 5: Chapter 1. Er-A570 Srn (In-Line) System Configuration

    3) ER-A57R1: Option device control ROM (1 chip) • 3) ER-A57R1: Option device control ROM (1 chip) The ROM chip (ER-A57R1) is installed on the main PWB of ER- • A570. The ROM chip (ER-A57R1) is installed on the main PWB of ER- A570.

  • Page 6: Chapter 3. Transmission System Specifications

    3. Components MANE PARTS CODE Q’ty PWB UNIT CPWBX7317RC01 PWB BRACKET LANGT7466RCZ Z CONNECTOR BRACKET LANGT7510RCZ Z SCREW (FOR HOLDING OF THE PWB AND PWB BRACKET) LX –BZ6665RCZZ SCREW (FOR : PWB BRACKET AND PWB BRACKET, PWB BRACKET AND MAIN CHASSIS, LX–BZ6774R CZZ GND WIRE.) WIRING TIE...
  • Page 7 8 Bits  Γ Closing flag (8 Bits) (01111110) (7E) Two types of packet formats are available for the SHARP RETAIL 8 Bits NETWORK. One is the data packet (the content of data is judged by the host level). The other is the control packet which is responded to Fig.
  • Page 8 Communication is disabled due to full retry counts . . . "PW-OFF" DATA PACK NRDY (power off) will be printed on the master unit. packet packet packet (Not ready) 4 Abnormal sequence-3 (when ACK is in error) packet Data (No ACK) CH NO CH NO CH NO...

  • Page 9: Chapter 4. File/Data Allocation In The In-Line System

    CHAPTER 4. FILE/DATA ALLOCATION IN THE IN-LINE SYSTEM Master Satellite ∗ 1 ; In case of system report job disable on back-up master, consolidation and receive files need not be created in back-up master. ∗ 2 ; The clerk totalizer file only need to have one blocks. Preset ∗...
  • Page 10 2. Down-Loading Job List 3. Key operation List of Down load jobs 1) Down-loading of PGM-mode program data on DEPT/PLU Mode Item Note (a) Down-loading to all the satellites in the system SRV parameter Including the machine parameter relating to 1 item inline operations.

  • Page 11: Chapter 6. Srv-Mode Programming

    CHAPTER 6. SRV-MODE PROGRAMMING (JOB#) ABCD M: Master S: Satellite Job# Item Key sequence #902 MRS = 0000 902-A: 1. Choice of inline 1. Inline 902-A #918 MRS = 0000 918-A: 1. Printing of text of a tied PLU in set 1.
  • Page 12 Job# Item Key sequence #920 MRS = 0000 920-A: 1. Buck up master function 1. Buck up master function 920-A Exit 920-B: 1. System report and down load job is 1. System 2. The GLU 3. The clerk executed in the buck up master report and finalization system...
  • Page 13 Job# Item Key sequence #924 MRS = 0000 924-B: 1. Save file except for PLU 1. Save file 2. Locking 3. Locking 2. Programming whether or not to lock except for after clerk after term REG mode entries after individual 924-B resetting clerk...
  • Page 14 Job# Item Key sequence #925 MRS = 0000 925-D: 1. PLU stock control system 1. PLU stock 2. Resetting in 2. Resetting in the open store state. control the open 925-D system store state Disable Centralized Enable Disable Individual Enable <<Detailed descriptions of the parameter for Job #925>>...
  • Page 15 Job# Item Key sequence #926 MRS=0004 926-A: 1. Sending "last void data" on KP 1. Sending "last 2. Sending "past 2. Sending "past void data" on KP void data" on void data" on 926-A 926-B: 1. Program reset in PGM2 mode 1.
  • Page 16 Job# Item Key sequence #899 Clearing the memories for inline operations. • Function This operation clears all the inline program data memory and work memory. After carrying out this clearing operation, any inline communication is inhibited until the necessary data for inline operations are re-programmed.

  • Page 17: Chapter 7. Pgm2 Mode Programming

    CHAPTER 7. PGM2 MODE PROGRAMMING Job# Item Key sequence • #3610 Terminal number 3610 NK: Terminal No. = 0 ~ 254 • #3611 Master list (Generation) 3611 NK1: Terminal No. = 1 ~ 254 NK2: Register No. = 1 ~ 999999 •...
  • Page 18 Job# Item Key sequence • #3654 K.P. name Space 3654 TEXT NK 1: K.P. No. = 1~9 TEXT: Max. 12character • #3655 Print format for K.P. 0000 3655 PLU/DEPT code Amount Print Print Skip Skip Unit price Print Skip • #3610 Inline preset reading 3610...
  • Page 19 CHAPTER 8. TROUBLE SHOOTING JOBS : Master : Satellite BM : Backup master JOB# ITEM MODE KEY SEQUENCE 5810 #5810 Master declaration PGM2 BM/M 5820 #5820 Recover declaration PGM2 BM/M 5940 #5940 Clerk preset file in use flag foreed to clear PGM2 5990 #5990...

  • Page 20: Chapter 9. Reading (X) And Resetting (Z) Reports

    (4) Syetem sales report for master/backup master CHAPTER 9. READING (X) AND MODE ∗1 RESETTING (Z) REPORTS ∗3 DATA FOR OP X/Z X1/Z1 X2/Z2 REPORT NAME JOB# READING NOTE (1) Job #Ynm: Y = 1 when the master is in the X1/Z1 mode. Φ...
  • Page 21 (5) Individual report jobs for the master/backup master/satellite MODE ∗1 ∗3 DATA FOR OP X/Z X1/Z1 X2/Z2 REPORT NAME JOB# READING NOTE Φ Φ Φ Φ GENERAL — Φ Φ DEPT/GROUP — Φ Φ IND. GROUP GROUP No Φ Φ GROUP TOTAL —...

  • Page 22: In-Line System

    CHAPTER 10. SOFTWARE INSTALLATION PROCEDURE FOR IN-LINE SYSTEM 1. SATELLITE 902 → • → ⊗ → 1XXX → TL ; INLINE YES 920 → • → ⊗ → 1 → TL ; SATELLITE MACHINE. 899 → • → ⊗ → TL ;...
  • Page 23 II. RS-232 SYSTEM FOR ER-A570 ER-A5RS ER-A57R1 (For ER-A570) MODEL (OPTION FOR ER-A570) CONTENTS CHAPTER 1. GENERAL ..........2-2 CHAPTER 2.

  • Page 24: Chapter 1. General

    CHAPTER 1. GENERAL Start-bit Data-bit Parity-bit Stop-bit This option (ER-A57R1 and ER-A5RS) is the RS-232 interface option for the ER-A570 cash register. It enables the ER-A570 to perform on-line data communications. j) Protocol : Polling/selecting (Simple procedure) When this option is used for on-line data communications, the ER- k) Transmission line : A570 can be connected to a host computer.

  • Page 25: Chapter 4. Block Diagram And System Configuration

    (The on-line option is not usable if the ER-A570 is an in-line satellite.) 1 Direct connection a) One-to-one connection Satellite Host computer ER-A570 The ER-A57R1 and ER-A5RS are Installed in ER-A570. (The same applies to the sample connections shown below.) 2 Connection via modems a) One-to-one connection Satellite Host computer...
  • Page 26 CHAPTER 5. SIGNAL CONNECTION 25PIN D-SUB 9PIN D-SUB SATELLITE HOST 25PIN D-SUB 9PIN D-SUB MODEM TERMINAL FRAME GROUND is connected to the shield of the cable. SD : TRANSMITTED DATA RD : RECEIVED DATA DTR : DATA TERMINAL READY FRAME GROUND is connected DSR : DATA SET READY to the shield of the cable.
  • Page 27 2. Connection between the terminal and MODEM SD : TRANSMITTED DATA RD : RECEIVED DATA DTR : DATA TERMINAL READY DSR : DATA SET READY Host Satellite ( 1 ) Inquines of the satellite. ( 2 ) Receives ENQ. Dummy Terminal No.

  • Page 28: Chapter 6. Rs-232 Protocol

    Host Satellite ( 1 ) Inquines of the satellite. ( 2 ) Receives ENQ. Dummy Terminal No. Checks the terminal No. (3bytes) (6bytes) to see if it is its own. ( 4 ) Receives ACK. ( 3 ) Sends ACK. ( 5 ) Sends the text.block.
  • Page 29 Host Satellite Continued from the ( 12 ) Sends text corresponding preceding page. to the job code. Start code Text (parameter) End code Two types of text block formats are available. ( 13 ) Receives text. Checks the check sum, text lingth, text data, etc. And goes to (15) if there is no error in them.

  • Page 34: Chapter 7. Control Signal Sequence

    CHAPTER 7. CONTROL SIGNAL SEQUENCE 1. Online transmission 1) Half duplex transmission 2) Full duplex transmission DATA DATA DATA DATA < 100ms < 100ms < 500ms < 500ms *Note : In the direct connect mode, same as full duplex control, but the CI signal is not controlled.
  • Page 35 4) Transmission sequence flow LINE ESTABLISHED FULL DUPLEX ? DCD OFF ? TIME OUT ? 5 sec RTS ON DSR ON ? FULL DUPLEX ? DCD ON ? TIME OUT ? 30 sec CTS ON ? TIME OUT ? 7 sec DTR OFF RTS OFF FULL...
  • Page 36 5) Receiving sequence flow LINE ESTABLISHED DSR ON ? HALF DCD ON ? TIME OUT ? DUPLEX ? ID. ENQ ∞ 30sec ACK or NAK 4 sec RXRDY ? TIME OUT ? TEXT 7 sec SEND TEXT READ 1 CHARACTER LINE ESTABLISHED EOT ? DTR OFF...

  • Page 37: Chapter 8. Data Block Format

    CHAPTER 8. DATA BLOCK FORMAT Example Memory image 1. Basic format 1) ID-ENQ : 10bytes Line image ENQ code (05h) Terminal No. 000001-999999 (6 bytes) Transmission sequence EOT is set as dummy cahracters. (3 bytes) 2) ACK : 1 byte 06h 3) NAK : 1 byte 15h CHAPTER 9.
  • Page 38 [JOB#6111] MRS = 00 Porgramming of the modem control 6111 6111-A: 1. Sensing of the CI signal Yes/No 1. Sensing of the CI signal 6111-A 6111-B: 1. Duplex type 1. Duplex type 6111-B Full duplex system Half duplex system [JOB#6112] MRS = 5 Programming of the transmission bau rate 6112 6112-A: Transmission bau rate...

  • Page 39: Iii. Test Function For Er-A6In And Er-A5Rs

    III. TEST FUNCTION FOR ER-A6IN AND ER-A5RS CHAPTER 1. General CHAPTER 4. Test Job & Code 1 RS-232 I/F check This test program, is contained in the ER-A57R1 (option ROM), has been developed for the purpose of confirming the operations of the JOB & CODE Contents...
  • Page 40 4 Release $FF. The program is terminated after the above contents are printed. Note) The above check should be made with the baud rate set at RS-232 channel setting (SW OFF: 1, SW ON: 0) 9600BPS. ∗ Refer to the silk print on the I/F board. Check 3 Timer check Before making check 2 , set the corresponding timer at ER-A5RS CN2...
  • Page 41 b6: n unexpected interruption is made. CHAPTER 7. INLINE CHECK b7: An error occurs. (Always 1 when in error print) δ Error print by diag 5 command The table below shows the names of the signals to be checked 1. IRC TEST 1 and their directions.
  • Page 42 2. IRC test 2 (FLAG send) 4. IRC test 4, 5 (Data transmission test) 1 Getting started This test is intended to perform data transmission test in an actually Get started with JOB #601. configured system. The system to be tested is composed of one set of master machine (set by JOB #604) and max.
  • Page 43 With the above procedure, setting and starting of the satellite c. The master receives the data and then checks the sequence machine to be tested are finished, and the master machine is No. and 0AAH data. ready for starting. If there are two or more satellite machines, steps a and b are Data transmission with the master is performed and the sequence repeated.

  • Page 44: Iv. Hardware Description For Er-A6In And Er-A5Rs

    Address Bus A2 Fig. 1 SRN controller board block diagram Address Bus A3 Fig. 1 shows the block diagram of the controller board of the SHARP RETAIL NETWORK. The Controller is connected to the system bus of Address Bus A4 the host system as one of I/O.
  • Page 45 Clock dividing circuit 2) Internal functions This block divides the blocks according to the CLK supplied from (1) Data handshaking circuit outside to generate the clock for CPU, DMAC and CTC and the Is used because data processing speeds vary and the timing of the E and transmission clock rate (480 KBPS or 1 MBPS selectable) HOST CPU and SUB CPU do not synchronize, the MB62H149 is for the ADLC.
  • Page 46 3) Terminal Name and Description (MB62H149) Terminal Host/ Description name IO/WR I/O write IO/RD I/O read 23.9 ± 0. 6 Address enable from DMAC Address strobe from DMAC Terminal count DAK23 DMA acknowledge 2+3 DRQRS DMA request read to sub DRQWS DMA request write to sub Host...
  • Page 47 • HOST read timing. 4) Pin Assingment and timing Charts Pin function will be described for the host and sub system. (1) Host pin description DB0—DB7 (data bus) Input/Output, 3-state Pins 54—61 These lines (data bus) are use for hardware flag assignments: 8-bit data write, hardware flag recognition, and 8-bit data read from the host.
  • Page 48 Λ WRS (Write from sub), Input DRQRS (DMA request read to sub CPU), Output Pin 6 Pin 42 Data write signal received from the subsystem (Z-80A) which is An active low DMA request to the sub CPU to read data which is used to create I/O and memory data write control signal.
  • Page 49 • Ψ RTS (Request to send), Input (for SRN) Sub CPU write timing Pin 68 An input from the link controller (ADLC) which becomes active low during transmission. The controller uses it for controlling the A0, A1, A4, A5 collision detect circuit and modem circuit. Ζ...
  • Page 50 • • Collision generation time TCOL TCOL Fig. 15 • A8, A9, A10, A15 timings Φ Fig. 20 4. Description of the DMA controller (DMAC; µPD8257-2) TSDG TSDH The µPD8257 DMAC is a signal-chip, programmable DMA controller D0-D7 designed to control DMA transfers between the I/O devices and TADG memory.
  • Page 51 2) Actual DMAC Operations Address bus Memory Data bus CP U (Z-80) External I/O device BUSRQ device BUSAK DMA C (8257) Fig. 23 Transfer from memory to I/O device 1 When the CPU wants to start a DMA cycle, it sets the number of bytes to be transferred and the first address of the tansfer memory area into the registers within the DMAC.
  • Page 52 3) DMAC (8257-2) Pin Functions Pin No. Signal name/in-out/Description I/OR (I/O Read) – Active Low Input/output (3 state) This pin functions as an input when is Slave mode. Application of a Low level to this pin reads the 8-bit status register value or the upper/lower byte of the 16-bit DMA address register or 16-bit TC regsiter.
  • Page 53 Pin No. Signal name/in-out/Description 30 – 26 DO-D7 (Data Bus) – Input/output (3 state) When the µPD8257 is programmed by the CPU (Z-80), the data bus accepts the upper/Lower byte of DMA address and 23 22, 21 TC register value output from the CPU, or 8-bit data to be loaded into the Mode Set register (Slave mode). When the CPU wants to read the value of the DMA address register, TC register, or status register, the data bus is used to transfer the pertinent data value to the CPU (Slave mode).
  • Page 54 Input/ Pin No. Symbol Pin name and function Output Ground pin – This pin indicates that send data exists in the TxFIF0. If CR2b7 is set to one, this output is set to Low. This pin is set to High when a Close flag has been transmitted after a frame is completed, an Abort is transmitted, CR2b7 is reset in the Mark Idle state (RTS remains at Low if CR2b7 is reset to zero in any state other than the Mark Idle state), or the RESET input is held at Low.
  • Page 55 Input/ Pin No. Symbol Pin name and function Output LOC/DTR Loop On Line Control/Data Terminal Ready output. This pin functions as the DTR in any mode other than Loop mode (CR3b5 = 0). It is set Low if CR3b7 is set to one, and is set High when the same bit is set to zero.
  • Page 56 of the following transistor (IC7) is set Low, it is turned off. 3) Pin Configuration (top view) When hte RTS is set Low, transistor Q1 turned on through an inverter, which applies a bese current to Q2, turnit it on. When Q2 and pins 10 and 9 of IC7 are turned on, the output transistors IC7 (pins 6 and 5) are turned on.
  • Page 57 3 ER-A57R1 ........
  • Page 58 b) Connecting the oscillator and its adjustment Key operations: MODE switch: SRV position Connect a dummy network or branch-trunk network on to the output of the ER-A6IN installed in the ER-A570, and connect the oscillator to the dummy or branch-trunk network. iii) Checking transmitter terminals’...

  • Page 59: Circuit Diagram

    12. Circuit diagram 4 ™ 16...
  • Page 60 4 ™ 17...
  • Page 61 ER-A6IN OPTCN1 OPTCN2 IRCCN SIGNAL SIGNAL No. No. SIGNAL SIGNAL No. No. SIGNAL (φ) (φ) BREQ BACK BREQ TRQ2 BACK TRQ2 TRQ1 EXINT1 TRQ1 EXINT0 EXINT1 TRRQ EXINT0 RSRQ TRRQ RFSH RSRH IPLON RFSH IPLON POFF VRAM POFF (+12V) VRAM +24V (+12V) +24V...
  • Page 62 13. PWB layout 1 Parts side 4 ™ 19...
  • Page 63 2 Solder side 4 ™ 20...

  • Page 64: Block Diagram

    CHAPTER 2. ER-A5RS 3. Description of main LSI 3-1. OPC1 (F256004PJ) 1. General 1) General description The ER-A5RS is composed of the following blocks: The OPC1 is a gate array of integrated peripheral circuits of RS- 232/Simple IRC interface. 1) RS-232 receiver (75189A) One chip of the OPC1 is equipped with four communication circuits.
  • Page 65 3) Block diagram TO/FROM USART TCR0 Inline cont Data bus buffer Timer0 control RCVDT0 Timer0 TCR1 Read/write Timer1 control RCVDT1 control Timer1 TCR2 Decorder control Timer2 control RCVDT2 Timer2 SL00 SL01 TCR3 SL02 SL10 SL11 Timer3 control SL12 RCVDT3 CHSL SL20 SL21 SL22...
  • Page 66 4) Pin description OPC1 pin table The signals marked with "-" at the end are LOW active signals. Example: "CS1-" = "CS1" Pin No. Pin name ER-A5RS Description SL00 SL00 RS-232/UNIT0 channel select SL01 SL01 SL02 SL02 SL10 SL10 RS-232/UNIT1 channel select SL11 SL11 SL12...
  • Page 67 Pin No. Pin name ER-A5RS Description TRQ2- TIMER IRQ signal (INLINE) DATA BUS (MAIN) DATA BUS (USART) ADDRESS BUS (MAIN) OPTCS- OPTCS- OPTION CHIP SELECT (from MAIN) RDO- RDO- READ signal (from MAIN) WRO- WRO- WRITE signal (from MAIN) RES- RES- RESET signal (from MAIN) READ signal (To USART)
  • Page 68 Operations in the advancement synchronization mode 3-2. USART (MB89371A) • Detection of framing error, overrun error, parity error 1) General • Transmission/reception buffer state acknowledgment The MB89371A (Serial data transmitter/receiver, 2 units) is a versa- • tile-use interface LSI for communication lines, which is equipped with Break characters detection two sets of equivalent units of the MB89251A (serial data transmit- Error start bit detection...
  • Page 69 4) Pin description Pin No. Pin name ER-A5RS Data bus RCVDT1 RCVDT1 RS-232 reception data signal RCVDT2 RCVDT2 – TRNCLK1- Data transmission clock TRNCLK2- Write signal CS1- CS1- RS-232 chip select CS2- CS2- RSLCT0 Address bus RSLCT1 Read signal RCVRDY1 RCVRDY1 RS-232 data reception enable signal RCVRDY2...
  • Page 70 Potential at point a changes according to a fluctuation in the 4. Power supply circuit +12V output. Waveform at point a differs depending on the state The ER-A550 supplies +5V to +24V, and ±12V is generated from of +12V output. Χ...
  • Page 71 6. Circuit diagram...
  • Page 72 ER-A5RS OPTCN1 OPTCN2 RSCN1 SIGNAL No. No. SIGNAL SIGNAL No. No. SIGNAL SIGNAL (φ) (φ) BREQ BACK BREQ TRQ2 BACK TRQ1 TRQ2 EXINT1 TRQ1 EXINT0 EXINT1 RSCN2 TRRQ EXINT0 SIGNAL RSRQ TRRQ RFSH RSRQ IPLON RFSH IPLON POFF VRAM POFF (+12V) VRAM (+12V)
  • Page 73 7. PWB layout 4 ™ 30...

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