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5
ICH7
GPIO
Alt Func
PIN
I/O/NC
POWER
GPIO0
Unmultiplexed AB18
I/O
CORE
GPIO1
REQ5#
C8
I/O
CORE
GPIO2
PIRQE#
G8
I/OD
CORE
GPIO3
PIRQF#
F7
I/OD
CORE
D
GPIO4
PIRQG#
F8
I/OD
CORE
GPIO5
PIRQH#
G7
I/OD
CORE
GPIO6
Unmultiplexed
AC21
I/O
CORE
GPIO7
Unmultiplexed
AC18
I/O
CORE
GPIO8
Unmultiplexed
E21
I/O
Resume
GPIO9
Unmultiplexed
E20
I/O
Resume
GPIO10
Unmultiplexed
A20
I/O
Resume
GPIO11
SMBALERT#
B23
I/O
Resume
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GPIO12
Unmultiplexed
F19
I/O
Resume
GPIO13
Unmultiplexed
E19
I/O
Resume
GPIO14
Unmultiplexed
R4
I/O
Resume
GPIO15
Unmultiplexed
E22
I/O
Resume
GPIO16
Unmultiplexed
AC22
I/O
CORE
C
GPIO17
GNT5#
D8
I/O
CORE
GPIO18
Unmultiplexed AC20
I/O
CORE
GPIO19
SATA_1GP
AH18
I/O
CORE
GPIO20
Unmultiplexed
AF21
I/O
CORE
GPIO21
SATA_0GP
AF19
I/O
CORE
GPIO22
REQ4#
A13
I/O
CORE
GPIO23
LDRQ_1#
AA5
I/O
CORE
GPIO24
Unmultiplexed
R3
I/O
Resume
GPIO25
Unmultiplexed
D20
I/O
Resume
GPIO26
Unmultiplexed
A21
I/O
Resume
GPIO27
Unmultiplexed
B21
I/O
Resume
GPIO28
Unmultiplexed
E23
I/O
Resume
B
GPIO29
OC5#
C3
I/O
Resume
GPIO30
OC6#
A2
I/O
Resume
GPIO31
OC7#
B3
I/O
Resume
GPIO32
Unmultiplexed
AG18
I/O
CORE
GPIO33
Unmultiplexed
AC19
I/O
CORE
GPIO34
Unmultiplexed
U2
I/O
CORE
GPIO35
SATACLKREQ#
AD21
I/O
CORE
GPIO36
SATA2GP
AH19
I/O
CORE
GPIO37
SATA3GP
AE19
I/O
CORE
GPIO38
Unmultiplexed
AD20
I/O
CORE
GPIO39
Unmultiplexed
AE20
I/O
CORE
GPIO48
GNT4#
A14
I/O
CORE
GPIO49
CPUPWRGD
AG24
I/O
V_CPU_IO
A
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
5
4
PU
SMI
TOL
DEFAULT
SIGNAL NAME
N
Y
3.3V
GPI
GPI0(pull high)
N
Y
5V
GPI
PREQ#5
N
Y
5V
GPI
GPIO2(pull high)
N
Y
5V
GPI
GPIO3(pull high)
N
Y
5V
GPI
GPIO4(pull high)
N
Y
5V
GPI
GPIO5(pull high)
N
Y
3.3V
GPI
ATADET0
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
Native
STRAPPED HI
N
Y
3.3V
GPI
SIO_PME#
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
GPI
STRAPPED HI
N
Y
3.3V
GPI
STRAPPED HI
N
N
3.3V
GPO
NC
N
N
3.3V
GPO
STRAPPED L
N
N
3.3V
GPO
NC
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
GPO
NC
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
Native
STRAPPED HI
N
N
3.3V
Native
STRAPPED HI
N
N
3.3V
GPO
NC
Y
N
3.3V
GPO
GPIO25(high 7507,low 7398)
N
N
3.3V
GPO
USB_EN
N
N
3.3V
GPO
NC
N
N
3.3V
GPO
NC
N
N
3.3V
GPI
USB_OCP#2
N
N
3.3V
GPI
USB_OCP#3
N
N
3.3V
GPI
USB_OCP#3
N
N
3.3V
GPO
BIOS_WP#(fill with 1)
N
N
3.3V
GPO
NC
N
N
3.3V
GPO
NC
N
N
3.3V
GPO
NC
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
GPI
STRAPPED HI
N
N
3.3V
Native
STRAPPED HI
N
N
V_CPU_IO
Native
H_PWRGD
4
3
2
SIO Fintek71882FG(CONTINUE)
GPIO
Alt Func
PIN
GPIO0
VIDOUT0
49
GPIO1
VIDOUT1
50
GPIO2
VIDOUT2
51
GPIO3
VIDOUT3
52
GPIO4
VIDOUT4
53
GPIO5
VIDOUT5/SIC
54
GPIO6
SLOTOCC#
55
GPIO7
Turbo1#/WDTRST#
56
GPIO15
LED_VSB/ALERT#
64
GPIO16
LED_VCC/Turbo2#
65
GPIO20
PCIRST1#
74
GPIO21
PCIRST2#
75
GPIO22
PCIRST3#
76
GPIO23
RSTCON#
77
GPIO24
ATXPG_IN
78
GPIO32
PWROK
84
GPIO26
PWSIN#
80
GPIO27
PWSOUT#
80
GPIO30
S3#
82
GPIO31
PSON#
83
GPIO33
RSMRST#
85
RSMRST#
GPIO40
FANIN3
25
GPIO41
FAN_CTL3
26
FAN_CTL3(NC)
GPIO25
PME#
79
GPIO10
SPI_SLK/FANIN4
59
GPIO10(NC)
GPIO11
SPI_CS0#/FANCTL4
60
GPIO11(NC)
GPIO12
SPI_MISO/FANCTL1_1
61
GPIO12(NC)
GPIO13
SPI_MOSI/BEEP
62
GPIO14
FWH_DIS/WDTRST#/SPI_CS1#
63
GPIO42
IRTX
27
GPIO43
IRRX
28
GPIO17
66
PCI Config.
DEVICEMCP1 INT PIN REQ#/GNT#
IDSEL
CLOCK
PIRQ#A
PIRQ#B
PCI1
PREQ#0
AD16
PCI_CLK0
PIRQ#C
PGNT#0
PIRQ#D
PIRQ#B
PCI2
PIRQ#C
PREQ#1
AD17
PCI_CLK1
PIRQ#D
PGNT#1
PIRQ#A
JCI1
Chassis Intrusion
Open
Normal
(1-2)
Chassis Open
3
2
1
Usage
Input/Output
NOTES
MCH_BSEL0
O12
MCH_BSEL1
O12
MCH_BSEL2
O12
NC
O12
NC
O12
NC
I/OOD12t
GPO
I/OOD12t
WDTRST#
OD12-5v
LED_VSB
OD12
LED_VCC
OD12
PCIRST1#
OD12
PCIRST2#
O12
PCIRST3#
O12
RSTCON#
OD12
ATXPG_IN
AIN
PWROK
OD12
PWSIN#
INts5v
PWSOUT#
OD12
S3#
INts5v
PSON#
OD12-5v
OD12
FANIN3
INts5v
OD12-5v
PME#
OD12-5v
I/OOD12t
I/OOD12t
I/OOD12t
BEEP(NC)
OD24
GPIO14
I/OOD12t
IRTX
O12
IRRX
INts
NC
I/OOD12t
DDRII DIMM Config.
DEVICE
ADRRESS
CLOCK
P_DDR0_A/N_DDR0_A
DIMM A
A0H
P_DDR1_A/N_DDR1_A
P_DDR2_A/N_DDR2_A
P_DDR0_B/N_DDR0_B
DIMM B
A4H
P_DDR1_B/N_DDR1_B
P_DDR2_B/N_DDR2_B
JUMPER SETTING
JBAT1
(1-2)NORMAL
(2-3)CLEAR
Title
Title
Title
BIOS Request Form
BIOS Request Form
BIOS Request Form
Size
Size
Size
Document Number
Document Number
Document Number
C
C
C
MS-7529
MS-7529
MS-7529
Date:
Date:
Date:
Friday, May 16, 2008
Friday, May 16, 2008
Friday, May 16, 2008
1
D
C
B
A
Rev
Rev
Rev
1.1
1.1
1.1
Sheet
Sheet
Sheet
32
32
32
of
of
of
33
33
33
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