Dtmf Decoder Circuit; Regulator Circuits - Icom IC-RP1620 Service Manual

3-3-6 RECEIVER UNLOCK SENSOR CIRCUIT
3-4 DTMF DECODER CIRCUIT
(RX AND LOGIC UNITS)
(LOGIC-A UNIT)
When the PLL circuit is unlocked, IC3 (pin 13) becomes
"HIGH". The "HIGH" signal is applied to IC9 (pin 14) as
AF signals from the RX UNIT are fed to Q1 on the
an unlock signal on the LOGIC UNIT.
LOGIC-A UNIT through J5 and signals are amplified.
IC4 is an IC chip for the DTMF detector. An applied
3-3m7 PLL (TX UNIT)
double-tone signal is detected at IC4 and outputs
The PLL circuit, using a PLL IC (IC2) and dual modulus signals as a 4-bit binary code.
prescaler (lC3) on the TX UNIT, generates the transmit
IC4
frequency with a Col~itts VCO (Q1) on the T-VCO UNIT.
t
.
.
The PLL IC sets the dividing ratio based on serial data
from the CPU and controls the dual modulus prescaler.
The PLL IC compares the phases of a VCO signal with
the reference oscillator frequency and detects the out-
of-step phase. Then, the VCO signal is output from the
PLL IC (pin 16 and 17).
3-3-8 TRANSMITTER REFERENCE
OSCILLATOR CIRCUIT (TX UNIT)
CLDV
signal
(IC9)
W
signal
(ICQt
A 12.8 MHz reference frequency is produced by the
Fig. 4
oscillator (XI). The frequency is adjusted with R24. The
reference frequency is buffer-amplified at Q5 and
applied to the PLL IC (IC2, pin 2).
3.5 REGULATOR CIRCUITS
3-3-9 TRANSMITTER LOOP FILTER AND
The DC voltages are supplied from regulator circuits
DC-DC CONVERTER CIRCUITS corresponding to the voltages. They are regulated at
(TX AND T-DC-DC UNITS)
the following circuits using 13.8
v
DC.
Phase-detected signals from IC2 (pin 16 and 17) are
(1) 5 V REGULATOR (RX, TX, AND LOGIC UNITS)
converted to DC voltage by a loop filter consisting of an
5
v
DC are
by the following three-terminal
active filter (Q3, 04).
voltage regulators.
The frequency at which the VCO oscillates is controlled
by varactor diodes (Dl -04) on the T-VCO UNIT.
DC
voltage (PLL lock voltage) is provided through the
integrator circuit (R15, C70).
(2) 8 V regulator (RX AND TX UNITS)
The DC-DC converter circuit (IC1 and Q1) on the T-DC-DC
8 V DC are regulated by the three-terminal voltage
UNlT creates approximately 20 V DC from 5 V DC to
regulator.
obtain wide range lock voltages for the PLL circuits.
REGULATOR CIRCUITS
I
REGULATOR
UNIT
3-3.10 TRANSMITTER VCO CIRCUIT
(T-VCO UNIT)
The VCO circuit ((21, 01-04] generates the transmit
frequency and produces FM modulation. Strip lines are
used for stable oscillation over a wide frequency range.
Varactor diodes (Dl -D4) provide frequency control. The
buffer amplifier (Q2) protects the PLL output signal from
VCO oscillation. The signal is divided by 64 or 65 in
the dual modulus prescaler (1'23). The phase-divided
signal is output from IC3 (pin 5) and applied to the
PLL IC (IC2, pin 6).
1 C 8
TX
303-1 1 TRANSCEIVER UNLOCK SENSOR
CIRCUIT (TX AND LOGfC UNITS)
When the PLL circuit is unlocked, IC2 (pin 13) becomes
"HIGH". The "HIGH" signal is applied to IC9 (pin 15) as
an unlock signal on the LOGIC UNIT.
3 - 4
IC9
RX
From
REG-A
-
UNlT
13.8V
IC16
LOGIC
LOGIC
UNIT
Fig. 5