Pllcircuits - Icom IC-RP1620 Service Manual

3-3 PLL CIRCUITS
3-3-1 GENERAL
Each receiver and transmitter circuit has an independent
PLL circuit for controlling frequencies. All PLL circuits
are shielded and installed on the RX and TX UNITS.
PLL circuits steadily oscillate the transmit frequency and
the receive local frequency. The PLL output frequency is
controlled by the divided ratio (N-data) of the program-
mable divider.
3-3-2
RECEIVER PLL CIRCUIT (RX UNIT)
The PLL circuit, using a PLL IC (IC3) and dual modulus
prescaler (IC4) on the RX UNIT, generates the 1st LO
frequency with a Colpitts VCO (Ql) on the R-VCO UNIT.
The PLL IC sets the dividing ratio based on serial data
from the CPU and controls the dual modulus prescaler.
The PLL IC compares the phases of a VCO signal with
the reference oscillator frequency and detects the out-
of-step phase. Then, the VCO signal is output from
the PLL IC (pin 16 and 17).
3.3-3 RECEIVER REFERENCE OSCILLATOR
CIRCUIT (RX AND TX UNITS)
3.3-4 RECEIVER LOOP FILTER AND DC-DC
CONVERTER CIRCUITS
(RX AND R=DC-DC UNITS)
Phase-detected signals from IC3 (pin 16 and 17) are
converted to DC voltage by a loop filter consisting of an
active filter ((210, Q11).
The frequency at which the VCO oscillates is controlled
by varactor diodes (01-04) on the R-VCO UNIT. DC
voltage (PLL lock voltage) is provided through the
integrator circuit (R32, C110).
The DC-DC converter circuit (ICl and Q l ) on the R-DC-DC
UNIT creates approximately 20 V DC from 5V DC to obtain
wide range lock voltages for the PLL circuits.
3-3-5 RECEIVER VCO CIRCUIT (R-VCO UNIT)
The VCO circuit (Ql, Dl-D4) generates the receive
frequency. Strip lines are used for stable oscillation
over a wide frequency range. Varactor diodes (Dl -D4)
provide frequency control. The buffer amplifier ((22)
protects the PLL output signal from VCO oscillation.
The signal is divided by 64 or 65 in the dual modulus
prescaler (IC4). The phase-divided signal is output from
IC4 (pin 5) and applied to the PLL IC (IC3, pin 6).
A 12.8 MHz reference frequency is produced by the
oscillator (XI) on the TX UNIT. The frequency is adjusted
with R24. The reference frequency is buffer-amplified
at Q5 and applied to the PLL IC (IC3, pin 2) on the RX
UNIT.
PLL
CIRCUITS
T-VCO UNIT
TX
UNlT
LOGIC
UNIT
---
RX
UNlT
r---
1
TX
T-DC-DC UNlT
LOOP
L---
FILTER
T-VCO
m
TX,l?Bit PLL N-data SET
PLL reference frequency
DIP-SW (5kHz
or
12.5KHz)
RX,17Bit PLL N-data SET
DIP-SW
Ref PRESCALER
1/64,1/65
IC4
R-DC-DC..UNIT
R-VCO
m
Fig. 3