Akai pdp4225m Service Manual page 42

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ANALOG
DEVICES
Preliminary Datasheet_____ 3/26/2004
F E A T U R E S
Analog/HDMI Dual Interface
Supports High-Bandwidth Digital Content Protection
R G B to Y CbCr two-way color conversion
Automated clamping level adjustment
1.8/3.3V Power Supply
100-pin LQ FP Pb-Free Package
R G B and Y C bC r Output Formats
A nalog In te rfa ce
8-bit Triple Analog to Digital Converters
150 M SPS Maximum Conversion Rate
Macrovision Detection
2:1 Input Mux
Full Sync Processing
Sync Detect for "Hot Plugging"
Mid-Scale Clamping
D igital V id eo In te rfa ce
HDMI 1.0, DVI 1.0
150 MHz HDMI Receiver
Supports High-Bandwidth Digital Content Protection
(HDCP 1.1)
D igital A udio In te rfa ce
HDMI 1.0 compatible audio interface
S/PDIF (IEC90658 compatible) digital audio output
Multi-channel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD Monitor
GENERAL D ESCRIPTION
The A D 9880 offers designers the flexibility o f an analog interface
and High-Definition Multimedia Interface (HDMI) receiver
integrated on a single chip. Also included is support for High
bandwidth Digital Content Protection (HDCP).
Analog Interface
The A D 9880 is a complete 8-bit 150 M SPS monolithic analog
interface optimized for capturing Component Video (YPbPr) and
R G B graphics signals. Its 150 M SPS encode rate capability and
full power analog bandwidth o f 300 MHz supports all H DTV
formats (up to 1080p) and FPD resolutions up to SX G A (1280 x
1024 at 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8V and 3.3V power supply, analog input, and Hsync.
Three-state CM OS outputs may be powered from 1.8V to 3.3V.
The A D 9880's on-chip P L L generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 150 MHz.
Analog/HDMI Dual Display Interface
F U N C T IO N A L B L O C K D IA G R A M
P L L clock jitter is typically less than 500 ps p-p at 150 MHz. The
A D 9880 also offers full sync processing for composite sync and
Sync-on-Green (SO G ) applications.
Digital Interface
The A D 9880 contains a H DMI 1.0 compatible receiver and
supports all H D TV formats (up to 1080p) and display resolutions
up to SX G A (1280 x 1024 at 75 Hz). The receiver features an
intra-pair skew tolerance o f up to one full clock cycle. With the
inclusion o f HDCP, displays may now receive encrypted video
content. The A D 9880 allows for authentication o f a video receiver,
decryption o f encoded data at the receiver, and renewability o f that
authentication during transmission as specified by the HDCP 1.1
protocol.
Fabricated in an advanced CM OS process, the A D 9880 is provided
in a space-saving 100-lead LQ FP surface-mount plastic package
and is specified over the 0 °C to 70 °C temperature range.
O n e
T e c h n o lo g y
W a y ,
P .O
B o x
9 10 6 ,
T e l: 6 1 7 /3 2 9 -4 7 0 0
AD9880
N o rw o o d ,
M A 0 2 0 6 2 -9 1 0 6 ,
U S A
F a x: 6 1 7 -3 2 6 - 8 7 0 3

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