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EN 136
9.
FM23, FM24, FM33
9.3
VGA Connector Panel (Diagram VGA)
The Video Graphics Array (VGA) panel serves as an interface
between the peripheral VGA equipment (Receiver box, PC,
etc.) and the SCAVIO panel. Some specifications of this panel:
•
Two NVMs are present, which hold identification data for
the DDC line.
•
Further, there are buffers present for the incoming and
outgoing sync signals.
•
RC_OUT cinch for linking with other equipment.
•
Provision to terminate the incoming sync lines with 75 Ohm
via the EBOX_PRESENT line.
For a description, see the next "SCAVIO" chapter.
9.4
SCAVIO Panel (Diagrams SC)
The Scaler Control Audio Video Input Output (SCAVIO) panel
contains:
•
All the input connectors,
•
Analogue and digital video processing,
•
Scaler (co-processor)
•
Interface to the PDP,
•
Audio processing (excluding the audio amplifier),
•
OTC (main processor), and
•
RS232C in/out.
Note: There are two versions of this panel, a Basic and an
Enhanced version. Therefore, many components are not
mounted for the Basic version.
For the circuit description, we divide the board into the following
parts:
1. Supply
2. Video processing
3. Audio processing
4. Control
9.4.1
Supply
See figure "Power Supply Path" in paragraph "Power Supply
9.1.5".
9.4.2
Video Processing (Diagrams SC3, 4, 5, 6, 10, 11 and 12)
Introduction
analogue
digital
processing
processing
path
path
AV1
CVBS
7225
7280
SAA7118
2fH progressive
De-int.
AV2
YC
Dig.
Video
dec.
1fH
7025
sync.
15,6 KHz = 1fH
decoder
31,2 KHz = 2fH
switch
H+V sync
0375
NVM
DDC
TMDS
7170
DVI-d
7146, 7158
7088, 7090
YPbPr
AD9887
2fH
Video+
RGB
RGB
RGB
sync.
AV3
HD
switch
RGB
DECODER
RGB
Flex
VGA
2
NVM
DDC
VGA
1
NVM
TXD/RXD-PW
DDC
SWITCH
RS
(SW-
232
TXD/RXD-OTC
download)
! All Functional blocks shaded grey are required for
the"Basic Configuration".
The remainder is required for the "Enhanced Configuration".
Figure 9-14 Video path
Circuit Descriptions, List of Abbreviations, and IC Data Sheets
YUV
dig.
I2C BUS 3
MEMORY
7605
7656
7670
PW164
RGB
RGB
RGB
ADC
dig.
Pixelworks
dig.
dig.
EPLD
+
TMDS
I2C BUS 1
I2C BUS 2
CL 26532038_011.eps
This mainly consists of a small analogue processing part and a
bigger digital signal processing part.
The video inputs like CVBS, YC, High Definition RGB, or YUV
(1fH and 2fH), VGA, and DVI-D are received and processed.
The YPbPr (2fH) is discretely converted to RGB, whereas the
YCbCr (1fH) is processed in the SAA7118 Digital Video
decoder. The base-band video inputs (CVBS and YC) are
output from the digital video decoder as digital YUV, which are
then further processed by the Pixel Works Scaler.
The VGA signals are first AD converted and then processed by
the PW Scaler.
The digital input on the DVI is first decoded by the TMDS
decoder inside the AD9887 and then processed by the PW
Scaler.
The PW Scaler output is going through an EPLD and then via
the LVDS transmitter to the PDP (Plasma Display Panel) as
differential serial data. The PDP is based on ALiS (Alternate
Lighting of Surface) technology and is an interlaced display,
with separate ODD and EVEN fields to be displayed.
Analogue Video
This part describes the analogue video and synchronisation
path of all inputs, until it reaches the "analogue digital
converters" of either the AD9887 (ADC+TMDS Decoder) or the
SAA7118E (Digital Video Decoder).
In addition, the switching part is described and the necessary
control signals.
In principle, all video control functions are done by the Pixel
Works processor.
Note: This part also includes the VGA connector panel that is
mounted on top of the SCAVIO panel.
Inputs
There are five video inputs, which are divided in three types:
•
VGA (2fH): named VGA1 and VGA2. Both are 15-pole
SUB-D connectors for RGB and HV, and are situated on
the VGA connector panel. For automatic identification by a
PC, each VGA input is foreseen with a DDC NVM IC. VGA2
is set default as loop through of VGA1. In the Enhanced
version, VGA2 can be switched as output, via the control
signals VGA2_OUT and VGA2_EN.
•
YPbPr/RGB (combined 2fH and 1fH): named AV3 and
suitable for YCbCr/HD-YPbPr/HD-RGB + HV. These are
cinch inputs. YPbPr and RGB are seen as separate inputs
by the HW and must be properly selected by SW.
•
CVBS like (1fH): named AV1 for CVBS and AV2 for Y/C.
These are also cinch inputs.
Video Path
The 1fH signals (including YPbPr) are buffered (item 7113/21/
17) and go directly to a digital video processor, the SAA7118E
(item 7225 on diagram SC5), where they are converted into a
digital signal.
The 2fH signals are also buffered; both YPbPr (item 7074/84/
79) and RGB (item 7141/38/35) buffers get the same input
signals.
When YPbPr signals are connected, the correct input must be
selected, to get a picture with proper colours. Thus, the signals
must pass a video matrix (item 7088/90, see diagram SC3),
where they are converted into RGB. There are two matrices, an
to PDP
NTSC and an ATSC. With the MATRIX_SEL signal, the correct
LVDS
matrix is chosen (item 7089). The detection is done automatic,
by an algorithm in the EPLD.
After the matrix, the signals enter a clamp/blanking circuit
(7102/03/04 and 7100), for the removal of the residual sync
signals. The control is done via the lines HD_BLANKN and
to OTC (7383)
HD_CLAMPN coming from the EPLD.
All RGB signals come together at 4-pole switches (item 7146/
240402
58), one for each colour, where they are switched to the AD
converter item 7170 (R_ADC, G_ADC and B_ADC).
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