Post Codes - Acer ASPIRE 5252 Service Manual

Post Codes

These tables describe the POST codes and descriptions during the POST.
Post Code Range
Phase
SEC
PEI
DXE
BDS
SMM
S3
ASL
PostBDS
Reserved
SEC Phase POST Code Table
Functionality Name (Include\
PostCode.h)
SEC_SYSTEM_POWER_ON
SEC_BEFORE_MICROCODE_PATCH
SEC_AFTER_MICROCODE_PATCH
SEC_SETUP_CAR_OK
SEC_GO_TO_SECSTARTUP
SEC_GO_TO_PEICORE
PEI Phase POST Code Table:
Functionality Name (Include\
PostCode.h)
PEI_SIO_INIT
PEI_CPU_REG_INIT
PEI_CPU_AP_INIT
PEI_CPU_HT_RESET
PEI_PCIE_MMIO_INIT
PEI_NB_REG_INIT
PEI_SB_REG_INIT
PEI_PCIE_TRAINING
PEI_TPM_INIT
PEI_SMBUS_INIT
PEI_PROGRAM_CLOCK_GEN
PEI_MEMORY_INIT
PEI_MEMORY_INIT_FOR_CRISIS
PEI_MEMORY_INSTALL
PEI_SWITCH_STACK
Chapter 4
POST Code Range
0x01 - 0x0F
0x70 - 0x9F
0x40 - 0x6F
0x10 - 0x3F
0xA0 - 0xBF
0xC0 - 0xCF
0x51 – 0x55
0xE1 – 0xE4
0xF9 – 0xFE
0xD8 – 0xE0
0xE5 – 0xF8
Phase
SEC
SEC
SEC
SEC
SEC
SEC
Phase
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
PEI
Post
Code
1 CPU power on and switch to
Protected mode
2 Patching CPU microcode
3 Setup Cache as RAM
7 Cache as RAM test
9 Setup BIOS ROM cache
0A Enter Boot Firmware Volume
Post
Description
Code
70 Super I/O Initialization
71 CPU Early Initialization
72 Multi-processor Early Initial
73 HyperTransport Initialization
74 PCIE MMIO BAR Initialization
75 North Bridge Early Initialization
76 South Bridge Early Initialization
77 PCIE Training
78 TPM Initialization
79 SMBUS Early Initialization
7A Clock Generator Initialization
7E Memory Initial for Normal boot.
7F Memory Initial for Crisis Recovery
80 Simple Memory test
82 Start to use Memory
Description
163